AT42QT2161-MMU Atmel, AT42QT2161-MMU Datasheet - Page 20

• Manufacturer Part Number: AT42QT2161-MMU
• Description: IC TOUCH SENSOR 16KEY QFN M-MOD
• Manufacturer: Atmel
• Type: Capacitiver

Specifications of AT42QT2161-MMU

• Touch Panel Interface: 8, 2-Wire
• Number Of Inputs/keys: 16 Key, Slider
• Resolution (bits): 10 b
• Data Interface: I²C, Serial
• Voltage Reference: Internal
• Voltage - Supply: 1.8 V ~ 5.5 V
• Current - Supply: 1.14mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.5
4.6
20
Data Packet Format
Combining Address and Data Packets Into a Transmission
AT42QT2161
Figure 4-4.
All data packets are 9 bits long, consisting of one data byte and an acknowledge bit. During a
data transfer, the host generates the clock and the START and STOP conditions, while the
Receiver is responsible for acknowledging the reception. An acknowledge (ACK) is signaled by
the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA
line high, a NACK is signaled.
A transmission consists of a START condition, an SLA+R/W, one or more data packets and a
STOP condition. The wired-ANDing of the SCL line is used to implement handshaking between
the host and the device. The device extends the SCL low period by pulling the SCL line low
whenever it needs extra time for processing between the data transmissions.
Holding down either SCL or SDA for clock stretching or any other purpose will slow down the
operation of the QT2161. This stretching is used while QT2161 processes data just received, or
prepares data to send. QT2161 needs to clock stretch (see
complete certain actions before ACK of transfer. If SCL or SDA is continuously held low for more
than ~12 ms, this will be deemed as a error condition and the
Note: Each write or read cycle must end with a STOP condition. The QT2161 may not respond
correctly if a cycle is terminated by a new START condition.
SDA
SCL
START
Address Packet Format
Addr MSB
1
2
Addr LSB
7
Section 9.4 on page 45
I
2
C
-compatible unit reset.
R/W
8
ACK
9
9614A–AT42–08/10
for timing) to