XC3S200AN-4FT256I Xilinx Inc, XC3S200AN-4FT256I Datasheet - Page 50

• Manufacturer Part Number: XC3S200AN-4FT256I
• Description: IC FPGA SPARTAN 3AN 256FTBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S200AN-4FT256I

• Number Of Logic Elements/cells: 4032
• Number Of Labs/clbs: 448
• Total Ram Bits: 294912
• Number Of I /o: 195
• Number Of Gates: 200000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-LBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

18 x 18 Embedded Multiplier Timing
Table 37: 18 x 18 Embedded Multiplier Timing
DS557 (v4.1) April 1, 2011
Product Specification
Notes:
1.
2.
3.
4.
5.
Combinatorial Delay
T
Clock-to-Output Times
T
T
T
Setup Times
T
T
T
Hold Times
T
T
T
Clock Frequency
F
MULT
MSCKP_P
MSCKP_A
MSCKP_B
MSDCK_P
MSDCK_A
MSDCK_B
MSCKD_P
MSCKD_A
MSCKD_B
MULT
Symbol
The numbers in this table are based on the operating conditions set forth in
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
The PREG register is typically used when inferring a single-stage multiplier.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
Combinational multiplier propagation delay from the A and B inputs
to the P outputs, assuming 18-bit inputs and a 36-bit product
(AREG, BREG, and PREG registers unused)
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using the PREG
register
Clock-to-output delay from the active transition of the CLK input to
valid data appearing on the P outputs when using either the AREG
or BREG register
Data setup time at the A or B input before the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)
Data setup time at the A input before the active transition at the CLK
when using the AREG input register
Data setup time at the B input before the active transition at the CLK
when using the BREG input register
Data hold time at the A or B input after the active transition at the
CLK when using only the PREG output register (AREG, BREG
registers unused)
Data hold time at the A input after the active transition at the CLK
when using the AREG input register
Data hold time at the B input after the active transition at the CLK
when using the BREG input register
Internal operating frequency for a two-stage 18x18 multiplier using
the AREG and BREG input registers and the PREG output
register
(2,3)
(5)
(2,4)
(3)
(3)
Description
(4)
(4)
(4)
(4)
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Spartan-3AN FPGA Family: DC and Switching Characteristics
Table
10.
3.56
0.00
0.00
0.00
0.35
0.35
Min
–
–
–
0
-5
Max
4.36
0.84
4.44
280
Speed Grade
–
–
–
–
–
–
3.98
0.00
0.00
0.00
0.45
0.45
Min
–
–
–
0
-4
Max
4.88
1.30
4.97
250
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
50