XC6SLX45T-3FG484I Xilinx Inc, XC6SLX45T-3FG484I Datasheet - Page 46

• Manufacturer Part Number: XC6SLX45T-3FG484I
• Description: IC FPGA SPARTAN 6 484FGGBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXTr

Specifications of XC6SLX45T-3FG484I

• Number Of Logic Elements/cells: 43661
• Number Of Labs/clbs: 3411
• Total Ram Bits: 2138112
• Number Of I /o: 296
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Configuration Switching Characteristics
Table 46: Configuration Switching Characteristics
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Power-up Timing Characteristics
T
T
T
Slave Serial Mode Programming Switching
T
T
F
Slave SelectMAP Mode Programming Switching
T
T
T
T
T
T
F
F
Boundary-Scan Port Timing Specifications
T
T
T
T
T
F
F
F
BPI Master Flash Mode Programming Switching
T
T
PL
POR
PROGRAM
DCCK
CCO
SCCK
SMDCCK
SMCSCCK
SMWCCK
SMCKCSO
SMCO
SMCKBY
SMCCK
RBCCK
TAPTCK
TCKTAP
TCKTDO
TCKH
TCKL
TCK
TCKB
TCKAES
BPICCO
BPIICCK
(2)
(2)
/T
Symbol
(4)
CCKD
/T
/T
/T
SMCCKD
SMCCKW
SMCCKCS
PROGRAM_B Latency
Power-on-Reset
PROGRAM_B Pulse Width
DIN Setup/Hold, slave mode
CCLK to DOUT
Slave mode external CCLK
SelectMAP Data Setup/Hold
CSI_B Setup/Hold
RDWR_B Setup/Hold
CSO_B clock to out
CCLK to DATA out in readback
CCLK to BUSY out in readback
Maximum CCLK frequency (XC6SLX4, XC6SLX9,
XC6SLX16, XC6SLX25, XC6SLX25T, XC6SLX45,
XC6SLX45T, XC6SLX75, and XC6SLX75T only)
Maximum CCLK frequency (XC6SLX100 and
XC6SLX100T in x8 mode, XC6SLX150, and
XC6SLX150T only)
Maximum CCLK frequency (XC6SLX100 and
XC6SLX100T in x16 mode only)
Maximum Readback CCLK frequency (XC6SLX4,
XC6SLX9, XC6SLX16, XC6SLX25, XC6SLX25T,
XC6SLX45, XC6SLX45T, XC6SLX75, and XC6SLX75T
only)
Maximum Readback CCLK frequency (XC6SLX100,
XC6SLX100T, XC6SLX150, and XC6SLX150T only)
TMS and TDI Setup time before TCK
TMS and TDI Hold time after TCK
TCK falling edge to TDO output valid
TCK clock minimum High time
TCK clock minimum Low time
Maximum configuration TCK clock frequency
Maximum boundary-scan TCK clock frequency
Maximum AES key TCK clock frequency
A[25:0], FCS_B, FOE_B, FWE_B, LDC outputs valid
after CCLK falling edge
Master BPI CCLK (output) delay
Description
(3)
(1)
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
17.0/1.0 17.0/1.0 17.0/1.0 27.0/2.0
6.0/1.0
10/100
6.0/1.0
7.0/0.0
5/40
500
5.5
6.5
12
80
16
13
12
50
40
35
20
12
10
12
12
33
33
15
-3
4
2
6.0/1.0
6.0/1.0
7.0/0.0
10/100
5/40
Speed Grade
-3N
500
5.5
6.5
12
80
16
13
12
50
40
35
20
12
10
12
12
33
33
15
4
2
6.0/1.0
6.0/1.0
7.0/0.0
10/100
5/40
500
5.5
6.5
12
80
16
13
12
50
40
35
20
12
10
12
12
33
33
15
-2
4
2
8.0/2.0
8.0/2.0
9.0/2.0
10/130
5/40
500
-1L
5.5
17
50
26
25
17
25
20
20
17
21
21
18
18
20
5
4
4
8
2
ms, Min/Max
µs, Min/Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
MHz, Max
ms, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
Units
46