73S8023C-IM/F Maxim Integrated Products, 73S8023C-IM/F Datasheet - Page 14

• Manufacturer Part Number: 73S8023C-IM/F
• Description: IC SMART CARD INTERFACE 32-QFN
• Manufacturer: Maxim Integrated Products
• Type: Smart Card Interfacer

Specifications of 73S8023C-IM/F

• Controller Type: Smart Card Interface
• Interface: *
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Supply: 4.9mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

73S8023C Data Sheet
8.4 Deactivation Sequence (Asynchronous Mode)
Deactivation is initiated either by the system controller by setting CMDVCC high, or automatically in the
event of hardware faults. Hardware faults are over-current, overheating, V
extraction during the session.
The following steps list the deactivation sequence and the timing of the card control signals when the
system controller sets the CMDVCC high or OFF goes low due to a fault or card removal:
1. RST goes low at the end of time t
2. CLK stops low at the end of time t
3. I/O goes low at the end of time t
4. V
9 OFF and Fault Detection
There are two cases for which the system controller can monitor the OFF signal: to query regarding the
card presence outside card sessions, or for fault detection during card sessions.
Monitoring Outside a Card Session
In this condition, CMDVCC is always high, OFF is low if the card is not present, and high if the card is
present. Because it is outside a card session, any fault detection will not act upon the OFF signal. No
deactivation is required during this time.
Monitoring During a Card Session
time that OFF is set low, the sequencer starts the deactivation process.
Figure 8
outside the card session:
14
CMDVCC is always low, and OFF falls low if the card is extracted or if any fault is detected. At the same
CC
t
t
t
t
1
2
5
1
≥ 0.5 µs, timing by 1.5 MHz internal Oscillator
≥ 7.5 µs
= depends on V
+ t
is shut down at the end of time t
shows the timing diagram for the signals CMDVCC, PRES, and OFF during a card session and
CMDVCC
2
+ t
VCC
OFF
RST
CLK
I/O
3
+ t
4
t
+ t
3
≥ 0.5 µs
5
-- OR --
~= 100 µs
CC
Figure 7: Asynchronous Deactivation Sequence
filter capacitor.
t
4
t
1
≥ 0.5 µs
3
. Out of reception mode.
1
2
.
.
4
. After a delay t
t
2
t
3
5
(discharge of the V
t
4
DD
t
5
fault, V
CC
capacitor), V
CC
fault, and card
DS_8023C_019
CC
is low.
Rev. 1.5