73S8009C-32IM/F Maxim Integrated Products, 73S8009C-32IM/F Datasheet - Page 21

• Manufacturer Part Number: 73S8009C-32IM/F
• Description: IC PWR MGMT/SMART CARD INT 32QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S8009C-32IM/F

• Applications: Smart Card Reader, Writer
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 32-VFQFN Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS_8009C_025
3.6
The host controller is fully responsible for the activation sequencing of the smart card signals CLK, RST,
I/O, AUX1 and AUX2. All these signals are held low by the 73S8009C when the card is in the de-
activated state. Upon card activation (the fall of CMDVCC (#/%)), all the signals are held low by the
73S8009C until RDY goes high. The host should set the signals RSTIN, I/OUC, CLKIN, AUX1UC and
AUX2UC low prior to activating the card and allow RDY to go high before transitioning any of these
signals. In order to initiate activation, the card must be present and OFF must be high.
Deactivation is initiated either by the system controller by setting both CMDVCC (#/%) high, or
automatically in the event of hardware faults or assertion of the OFF_ACK signal. Hardware faults are
over-current, under-voltage, and card extraction during the session. The host can manage the I/O
signals, CLKIN, RSTIN, and CMDVCC (#/%) to create other de-activation sequences for non-emergency
situations.
The following steps show the deactivation sequence and the timing of the card control signals when the
system controller sets the CMDVCC(x)B high:
1. RST goes low at the end of time t1.
2. De-assert CLK at the end of time t2.
3. I/O goes low at the end of time t3. Exit reception mode.
4. De-assert internal VCC_ON at the end of time t4. After a delay, VCC is de-asserted.
Note: Since the 73S8009C does not control the waveshape of CLK (it is determined by the input form the
host CLKIN), there is no guarantee that the duty cycle of the last CLK high pulse will conform to duty
cycle requirements during an emergency deactivation.
Rev. 1.5
Activation and De-activation Sequence
CMDVCC5 or CMDVCC3
RSTIN
CLKIN
I/OUC
VCC
RDY
CLK
RST
I/O
I/O, AUX1, AUX2, CLK, RST are held LOW until RDY = 1 and CMDVCCx = 0
At t1 (50 ξs), if RDY=0 or overcurrent, circuit will de-activate (safety feature)
Figure 5: Activation Sequence
Ignored
Ignored
Ignored
t1
VCC valid
I/O = I/OUC if RDY=1
RST = RSTIN if RDY=1
CLK=CLKIN if RDY=1
73S8009C Data Sheet
21