ispPAC-POWR1014A-01TN48I Lattice, ispPAC-POWR1014A-01TN48I Datasheet - Page 33

• Manufacturer Part Number: ispPAC-POWR1014A-01TN48I
• Description: Supervisory Circuits ispPAC-POWR1014 w/ A DC I
• Manufacturer: Lattice
• Type: Power Supply Sequencer and Monitorr
• Series: ispPAC®r

Specifications of ispPAC-POWR1014A-01TN48I

• Internal Hysteresis: Yes
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Output Type: Open Collector / Drain
• Number Of Voltages Monitored: 10
• Monitored Voltage: Adj V
• Undervoltage Threshold: Adj
• Overvoltage Threshold: Adj
• Manual Reset: No
• Watchdog: No
• Power-up Reset Delay (typ): 500 ms
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 20 mA
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-48
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
Software-Based Design Environment
Designers can configure the ispPAC-POWR1014/A using PAC-Designer, an easy to use, Microsoft Windows com-
patible program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environment.
Full device programming is supported using PC parallel port I/O operations and a download cable connected to the
serial programming interface pins of the ispPAC-POWR1014/A. A library of configurations is included with basic
solutions and examples of advanced circuit techniques are available on the Lattice web site for downloading. In
addition, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer
operation. The PAC-Designer schematic window, shown in Figure 2-26, provides access to all configurable ispPAC-
POWR1014/A elements via its graphical user interface. All analog input and output pins are represented. Static or
non-configurable pins such as power, ground, and the serial digital interface are omitted for clarity. Any element in
the schematic window can be accessed via mouse operations as well as menu commands. When completed, con-
figurations can be saved, simulated, and downloaded to devices.
Figure 2-26. PAC-Designer ispPAC-POWR1014/A Design Entry Screen
In-System Programming
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The ispPAC-POWR1014/A is an in-system programmable device. This is accomplished by integrating all E
config-
uration memory and control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant
serial JTAG interface at normal logic levels. Once a device is programmed, all configuration information is stored
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on-chip, in non-volatile E
CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ispPAC-
POWR1014/A instructions are described in the JTAG interface section of this data sheet.
Programming ispPAC-POWR1014/A: Alternate Method
Some applications require that the ispPAC-POWR1014/A be programmed before turning the power on to the entire
circuit board. To meet such application needs, the ispPAC-POWR1014/A provides an alternate programming
method which enables the programming of the ispPAC-POWR1014/A device through the JTAG chain with a sepa-
rate power supply applied just to the programming section of the ispPAC-POWR1014/A device with the main power
supply of the board turned off.
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