LCMXO1200C-3TN144I Lattice, LCMXO1200C-3TN144I Datasheet - Page 3

• Manufacturer Part Number: LCMXO1200C-3TN144I
• Description: CPLD - Complex Programmable Logic Devices 1200 LUTs 113 IO 1.8 /2.5/3.3V -3 Spd I
• Manufacturer: Lattice

Specifications of LCMXO1200C-3TN144I

• Memory Type: SRAM
• Number Of Macrocells: 600
• Maximum Operating Frequency: 500 MHz
• Delay Time: 5.1 ns
• Number Of Programmable I/os: 113
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Supply Current: 21 mA
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Package / Case: TQFP-144
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 1.71 V
• Programmable Type: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Package: 144TQFP
• Family Name: MachXO
• Number Of Macro Cells: 600
• Maximum Propagation Delay Time: 5.1 ns
• Number Of User I/os: 113
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Ram Bits: 9420.8
• Operating Temperature: -40 to 100 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Introduction
Lattice Semiconductor
MachXO Family Data Sheet
The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flex-
ible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high-
security, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and
careful design will provide the high pin-to-pin performance also associated with CPLDs.
®
The ispLEVER
design tools from Lattice allow complex designs to be efficiently implemented using the MachXO
family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools
use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in
the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design
for timing verification.
1-2