LCMXO1200C-3TN144C Lattice, LCMXO1200C-3TN144C Datasheet - Page 95

• Manufacturer Part Number: LCMXO1200C-3TN144C
• Description: CPLD - Complex Programmable Logic Devices 1200 LUTS 113 I/O
• Manufacturer: Lattice

Specifications of LCMXO1200C-3TN144C

• Memory Type: SRAM
• Number Of Macrocells: 600
• Delay Time: 5.1 ns
• Number Of Programmable I/os: 113
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Supply Current: 21 mA
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Package / Case: TQFP-144
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 1.71 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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© 2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
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October 2005
For Further Information
A variety of technical notes for the MachXO family are available on the Lattice web site at www.latticesemi.com.
For further information on interface standards refer to the following web sites:
• MachXO sysIO Usage Guide (TN1091)
• MachXO sysCLOCK PLL Design and Usage Guide (TN1089)
• MachXO Memory Usage Guide (TN1092)
• Power Calculations and Considerations for MachXO Devices (TN1090)
• MachXO JTAG Programming and Configuration User’s Guide (TN1086)
• Minimizing System Interruption During Configuration Using TransFR Technology (TN1087)
• MachXO Density Migration (TN1097)
• IEEE 1149.1 Boundary Scan Testability in Lattice Devices
• JEDEC Standards (LVTTL, LVCMOS): www.jedec.org
• PCI: www.pcisig.com
6-1
MachXO Family Data Sheet
Supplemental Information
Further Information_01.1
Data Sheet