LC4064ZE-4TN48C Lattice, LC4064ZE-4TN48C Datasheet - Page 12

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LC4064ZE-4TN48C

Manufacturer Part Number
LC4064ZE-4TN48C
Description
CPLD - Complex Programmable Logic Devices 64MC 32 I/O Low Pwr 1.8V 4.7NS
Manufacturer
Lattice
Datasheet

Specifications of LC4064ZE-4TN48C

Memory Type
EEPROM
Number Of Macrocells
64
Maximum Operating Frequency
333.33 MHz
Delay Time
4.7 ns
Number Of Programmable I/os
32
Operating Supply Voltage
1.8 V
Supply Current
0.08 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-48
Mounting Style
SMD/SMT
Supply Voltage (max)
1.9 V
Supply Voltage (min)
1.7 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LC4064ZE-4TN48C
Manufacturer:
Lattice
Quantity:
250
Part Number:
LC4064ZE-4TN48C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
The number of BIE inputs, thus the number of Power Guard “Blocks” that can exist in a device, depends on the
device size. Table 8 shows the number of BIE signals available in the ispMACH 4000ZE family. The number of I/Os
available in each block is shown in the Ordering Information section of this data sheet.
Table 8. Number of BIE Signals Available in ispMACH 4000ZE Devices
Power Guard for Dedicated Inputs
Power Guard can optionally be applied to the dedicated inputs. The dedicated inputs and clocks are controlled by
the BIE of the logic blocks shown in Tables 9 and 10.
Table 9. Dedicated Clock Inputs to BIE Association
Table 10. Dedicated Inputs to BIE Association
For more information on the Power Guard function refer to TN1174,
Family.
Global OE (GOE) and Block Input Enable (BIE) Generation
Most ispMACH 4000ZE family devices have a 4-bit wide Global OE (GOE) Bus (Figure 11), except the ispMACH
4032 device that has a 2-bit wide Global OE Bus (Figure 12). This bus is derived from a 4-bit internal global OE
(GOE) PT bus and two dual purpose I/O or GOE pins. Each signal that drives the bus can optionally be inverted.
Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a
256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10
show a graphical representation of the global OE generation.
CLK0 / I
CLK1 / I
CLK2 / I
CLK3 / I
CLK/I
Dedicated Input
32 MC Block
0
1
2
3
4
5
6
7
8
9
ispMACH 4032ZE
ispMACH 4064ZE
ispMACH 4128ZE
ispMACH 4256ZE
A
A
B
B
Device
4064ZE Block
A
B
B
C
D
D
Two (Blocks: A and B)
Four (Blocks: A, B, C and D)
Eight (Blocks: A, B, C, …, H)
Sixteen (Blocks: A, B, C, …, P)
64MC Block
Number of Logic Blocks, Power
Guard Blocks and BIE Signals
12
A
B
C
D
4128ZE Block
G
B
C
D
F
H
ispMACH 4000ZE Family Data Sheet
Advanced Features of the ispMACH 4000ZE
128MC Block
4256ZE Block
D
H
A
E
D
G
G
M
O
O
E
B
J
L
256MC Block
H
A
P
I

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