A2F500M3G-FGG484 Actel, A2F500M3G-FGG484 Datasheet - Page 98

• Manufacturer Part Number: A2F500M3G-FGG484
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG484

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 204
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion DC and Switching Characteristics
Serial Peripheral Interface (SPI) Characteristics
Table 2-98 • SPI Characteristics
2- 86
Symbol
sp1
sp2
sp3
sp4
sp5
Notes:
1. These values are provided for a load of 35 pF. For board design considerations and detailed output buffer resistances,
2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the
use the corresponding IBIS models located on the Microsemi SoC Products Group website:
http://www.actel.com/download/ibis/default.aspx.
Microcontroller Subsystem User’s
Commercial Case Conditions: T
SPI_x_CLK minimum period
SPI_x_CLK = PCLK/2
SPI_x_CLK = PCLK/4
SPI_x_CLK = PCLK/8
SPI_x_CLK = PCLK/16
SPI_x_CLK = PCLK/32
SPI_x_CLK = PCLK/64
SPI_x_CLK = PCLK/128
SPI_x_CLK = PCLK/256
SPI_x_CLK minimum pulse width high
SPI_x_CLK = PCLK/2
SPI_x_CLK = PCLK/4
SPI_x_CLK = PCLK/8
SPI_x_CLK = PCLK/16
SPI_x_CLK = PCLK/32
SPI_x_CLK = PCLK/64
SPI_x_CLK = PCLK/128
SPI_x_CLK = PCLK/256
SPI_x_CLK minimum pulse width low
SPI_x_CLK = PCLK/2
SPI_x_CLK = PCLK/4
SPI_x_CLK = PCLK/8
SPI_x_CLK = PCLK/16
SPI_x_CLK = PCLK/32
SPI_x_CLK = PCLK/64
SPI_x_CLK = PCLK/128
SPI_x_CLK = PCLK/256
SPI_x_CLK, SPI_x_DO, SPI_x_SS rise time (10%-90%)
SPI_x_CLK, SPI_x_DO, SPI_x_SS fall time (10%-90%)
This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output
characteristics given for a 35 pF load on the pins and all sequential timing characteristics are related to
SPI_x_CLK. For timing parameter definitions, refer to
Description and Condition
Guide.
J
= 85ºC, VDD = 1.425 V, –1 Speed Grade
R e visio n 6
Figure 2-46 on page
1
1
A2F200
0.16
0.32
0.64
1.28
2.56
0.08
0.16
0.32
0.64
1.28
0.08
0.16
0.32
0.64
1.28
NA
NA
NA
4.7
3.4
40
80
20
40
20
40
2-87.
A2F500
0.16
0.32
0.64
1.28
2.56
0.08
0.16
0.32
0.64
1.28
0.08
0.16
0.32
0.64
1.28
4.7
3.4
20
40
80
10
20
40
10
20
40
SmartFusion
Unit
ns
ns
ns
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
us
ns
ns
ns
µs
µs
µs
µs
µs
ns
ns