AGLP060V5-CSG289 Actel, AGLP060V5-CSG289 Datasheet
AGLP060V5-CSG289
Specifications of AGLP060V5-CSG289
Related parts for AGLP060V5-CSG289
AGLP060V5-CSG289 Summary of contents
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... Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125. † The AGLP030 device does not support this feature. June 2010 © 2010 Actel Corporation Advanced I/O • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—4 Banks per Chip on All ® ...
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IGLOO PLUS Low Power Flash FPGAs 1 I/Os Per Package IGLOO PLUS Devices Package CS201 CS281 CS289 VQ128 VQ176 Note: When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number ...
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IGLOO PLUS Ordering Information _ AGLP125 V2 CS Package Type Supply Voltage 1.5 V only Part Number AGLP030 = 30,000 System Gates AGLP060 = 60,000 System Gates AGLP125 = 125,000 System ...
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... Temperature Grade Offerings Package CS201 CS281 CS289 VQ128 VQ176 Notes Commercial temperature range: 0°C to 70°C ambient temperature Industrial temperature range: –40°C to 85°C ambient temperature. Contact your local Actel representative for device availability: http://www.actel.com/company/contact/default.aspx AGLP030 AGLP060 – – – ...
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... Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-64 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-77 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-78 Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79 Package Pin Assignments 128-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 176-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 201-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 281-Pin CSP ...
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IGLOO PLUS Device Family Overview General Description The IGLOO PLUS family of flash FPGAs, based on a 130 nm flash process, offers the lowest power FPGA, a single-chip solution, small-footprint packages, reprogrammability, and an abundance of advanced features. ...
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... Live at Power-Up The Actel flash-based IGLOO PLUS devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based IGLOO PLUS devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs ...
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... The versatility of the IGLOO PLUS core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming ...
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... Flash*Freeze Mode Control Figure 1-2 • IGLOO PLUS Flash*Freeze Mode 1- 4 Bank 0 Flash*Freeze Charge Technology Pumps Bank 2 Figure 1-2 for an illustration of entering/exiting Actel IGLOO PLUS FPGA Flash*Freeze Pin R ev isio CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* I/Os VersaTile ...
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... X2 LUT-3 CLK Y X3 Figure 1-3 • VersaTile Configurations User Nonvolatile FlashROM Actel IGLOO PLUS devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • Internet protocol addressing (wireless or fixed) • System calibration settings • Device serialization and/or inventory control • ...
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IGLOO PLUS Device Family Overview SRAM and FIFO IGLOO PLUS devices (except AGLP030 devices) have embedded SRAM blocks along their north side. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and ...
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... Wide Range I/O Support Actel IGLOO PLUS devices support JEDEC-defined wide range I/O operation. IGLOO PLUS devices support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1. ...
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IGLOO PLUS DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of ...
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... All parameters representing voltages are measured with respect to GND unless otherwise specified ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel’s timing and power simulation tools. ...
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Table 2-4 • Overshoot and Undershoot Limits Average VCCI–GND Overshoot or VCCI as a Percentage of Clock Cycle 2 less 3 V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at 85°C. 2. The duration is ...
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... IGLOO PLUS DC and Switching Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels (see When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V for V5 devices, and 0.75 V ± ...
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VCC = VCCI + VT where VT can be from 0. 0.9 V (typically 0. VCC = 1.575 V Region 1: I/O Buffers are OFF VCC = 1.14 V Region 2: I/O buffers are ON. ...
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... IGLOO PLUS DC and Switching Characteristics Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. ...
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... VCCI, and VJTAG), operating temperature, system clock frequency, and power mode usage. Actel recommends using the Power Calculator and SmartPower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. Table 2-8 • ...
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IGLOO PLUS DC and Switching Characteristics Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Shutdown Mode Core Voltage Typical (25°C) 1 1.5 V Table 2-12 • Quiescent Supply Current (IDD), No IGLOO PLUS Flash*Freeze Mode 2 ...
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Power per I/O Pin Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger 2 3.3 ...
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IGLOO PLUS DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-15 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices For IGLOO PLUS Devices, 1.5 V Core Supply Voltage Parameter PAC1 ...
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... Notes: 1. This is the minimum contribution of the PLL when operating at lowest frequency. 2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or the SmartPower tool in Actel Libero Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 Devices, 1 ...
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... Bank quiescent power (VCCI-dependent) Notes: 1. This is the minimum contribution of the PLL when operating at lowest frequency. 2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or the SmartPower tool in Actel Libero IDE software. Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application ...
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F is the global clock signal frequency. CLK N is the number of VersaTiles used as sequential modules in the design. S-CELL and P AC1 AC2 AC3 AC4 Sequential Cells Contribution—P α ...
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IGLOO PLUS DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this ...
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User I/O Characteristics Timing Model I/O Module (Registered 1. Input LVCMOS 2 0.63 ns ICLKQ t = 0.18 ns ISUD Input LVTTL Clock Register Cell I/O ...
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IGLOO PLUS DC and Switching Characteristics PAD PAD Y GND Figure 2-4 • Input Buffer Timing Model and Delays (example CLK I/O Interface t = MAX(t (R ...
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DOUT D Q CLK D From Array I/O Interface t 50% D DOUT PAD Figure 2-5 • Output Buffer Model and Delays (example) IGLOO PLUS Low Power Flash FPGAs t DP DOUT t = MAX(t (R ...
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IGLOO PLUS DC and Switching Characteristics t EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD Vtrip D 50 EOUT (R) 50% EOUT t ZLS ...
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Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Equiv. Software ...
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IGLOO PLUS DC and Switching Characteristics Table 2-22 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V ...
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Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-23 • Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS ...
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IGLOO PLUS DC and Switching Characteristics Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade, Commercial-Case Conditions: T 3.3 V LVTTL / High 5 pF – 3.3 V LVCMOS 3.3 V LVCMOS ...
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Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade Commercial-Case Conditions: T 3.3 V LVTTL / High 5 pF 3.3 V LVCMOS 3.3 V LVCMOS 100 µ High 5 pF ...
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... These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend drive strength selection, temperature, and process. For board design considerations and detailed output buffer CCI resistances, use the corresponding IBIS model on the Actel website at http://www.actel.com/download/ibis/default.aspx (VOLspec (PULL-DOWN-MAX (VCCImax – ...
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Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values VCCI 3.3 V 3.3 V (wide range I/Os) 2.5 V 1.8 V 1.5 V 1.2 V 1.2 V (wide range I/Os) Notes (VCCImax ...
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... The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals ...
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Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-34 • Minimum and Maximum DC ...
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IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1 Core Voltage Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Drive Strength ...
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V LVCMOS Wide Range Table 2-40 • Minimum and Maximum DC Input and Output Levels Equivalent Software Default Drive 3.3 V LVCMOS Strength 1 Wide Range Option VIL Drive Min. Max. Strength V V 100 µ –0.3 ...
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IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1 Core Voltage Table 2-42 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Equivalent Software Default Drive ...
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Table 2-44 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Equivalent Software Default Drive Drive Strength Speed 1 Strength Option Grade t DOUT 100 µ STD 0.98 ...
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IGLOO PLUS DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2 extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. Table 2-46 • Minimum and Maximum DC Input and Output Levels ...
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Timing Characteristics Applies to 1 Core Voltage Table 2-48 • 2.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Drive Strength Speed Grade STD 6 mA STD 8 ...
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IGLOO PLUS DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output ...
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Timing Characteristics Applies to 1 Core Voltage Table 2-54 • 1.8 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Drive Strength Speed Grade STD 4 mA STD 6 ...
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IGLOO PLUS DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1 extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull ...
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Timing Characteristics Applies to 1 Core Voltage Table 2-60 • 1.5 V LVCMOS Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Drive Strength Speed Grade STD 4 mA STD Note: ...
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IGLOO PLUS DC and Switching Characteristics 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table ...
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V LVCMOS Wide Range Table 2-68 • Minimum and Maximum DC Input and Output Levels 1.2 V LVCMOS Wide 1 Range V IL Equivalent Software Default Drive Drive Strength Min. Max. 2 Strength Option V V 100 µA 2 ...
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IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1 Core Voltage Table 2-70 • 1.2 V LVCMOS Wide Range Low Slew – Applies to 1 Core Voltage Commercial-Case Conditions: T Equivalent Software Default Drive ...
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I/O Register Specifications Fully Registered I/O Buffers with Asynchronous Preset Preset PRE Data D C DFN1P1 CLK A Data Input I/O Register with: Active High Preset Positive-Edge Triggered Figure 2-12 • Timing Model of Registered I/O Buffers with Asynchronous Preset ...
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IGLOO PLUS DC and Switching Characteristics Table 2-72 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the ...
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Fully Registered I/O Buffers with Asynchronous Clear Data D CC DFN1C1 CLK AA CLR DD Data Input I/O Register with Active High Clear Positive-Edge Triggered Figure 2-13 • Timing Model of the Registered I/O Buffers with Asynchronous Clear Data_out Y ...
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IGLOO PLUS DC and Switching Characteristics Table 2-73 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the ...
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Input Register 50% 50% CLK t 50% 1 Data Preset Clear Out_1 Figure 2-14 • Input Register Timing Diagram Timing Characteristics 1 Core Voltage Table 2-74 • Input Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q ...
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IGLOO PLUS DC and Switching Characteristics 1 Core Voltage Table 2-75 • Input Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Input Data Register ICLKQ t Data Setup Time for the Input Data Register ...
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Output Register 50% CLK 50% 1 Data_out Preset Clear DOUT Figure 2-15 • Output Register Timing Diagram Timing Characteristics 1 Core Voltage Table 2-76 • Output Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the ...
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IGLOO PLUS DC and Switching Characteristics 1 Core Voltage Table 2-77 • Output Data Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register ...
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Output Enable Register 50% 50% CLK t OESUD 1 50% 0 D_Enable Preset Clear EOUT t OECLKQ Figure 2-16 • Output Enable Register Timing Diagram Timing Characteristics 1 Core Voltage Table 2-78 • Output Enable Register Propagation Delays ...
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IGLOO PLUS DC and Switching Characteristics 1 Core Voltage Table 2-79 • Output Enable Register Propagation Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Output Enable Register OECLKQ t Data Setup Time for the Output Enable Register ...
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VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The IGLOO PLUS library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the and ProASIC3/ ...
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IGLOO PLUS DC and Switching Characteristics Fanout = 4 Length = 1 VersaTile Net Length = 1 VersaTile Net Length = 1 VersaTile Net Length = 1 VersaTile 50 OUT GND (RR) VCC OUT Figure 2-18 • ...
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Timing Characteristics 1 Core Voltage Table 2-80 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Note: For specific junction temperature and voltage supply levels, refer to ...
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IGLOO PLUS DC and Switching Characteristics VersaTile Specifications as a Sequential Module The IGLOO PLUS library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this ...
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CLK t SUD 50% Data EN 50 PRE SUE CLR Out t CLKQ Figure 2-20 • Timing Model and Waveforms Timing Characteristics 1 Core Voltage Table 2-82 • Register Delays Commercial-Case Conditions: T ...
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IGLOO PLUS DC and Switching Characteristics 1 Core Voltage Table 2-83 • Register Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of the Core Register CLKQ t Data Setup Time for the Core Register SUD t Data Hold Time ...
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Global Resource Characteristics AGLP125 Clock Tree Topology Clock delays are device-specific. global tree presented in Figure 2- used to drive all D-flip-flops in the device. CCC Figure 2-21 • Example of Global Tree Use in an AGLP125 Device ...
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IGLOO PLUS DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and ...
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Table 2-86 • AGLP125 Global Resource Commercial-Case Conditions: T Parameter t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock RCKMPWH t Minimum Pulse Width Low ...
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IGLOO PLUS DC and Switching Characteristics Table 2-88 • AGLP060 Global Resource Commercial-Case Conditions: T Parameter t Input Low Delay for Global Clock RCKL t Input High Delay for Global Clock RCKH t Minimum Pulse Width High for Global Clock ...
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Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-90 • IGLOO PLUS CCC/PLL Specification For IGLOO PLUS devices, 1 Core Supply Voltage Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency ...
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IGLOO PLUS DC and Switching Characteristics Table 2-91 • IGLOO PLUS CCC/PLL Specification For IGLOO PLUS V2 Devices, 1 Core Supply Voltage Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in ...
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Output Signal Note: Peak-to-peak jitter measurements are defined by T Figure 2-22 • Peak-to-Peak Jitter Definition IGLOO PLUS Low Power Flash FPGAs T T period_max period_min = T – T peak-to-peak period_max period_min ...
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IGLOO PLUS DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM Figure 2-23 • RAM Models 2- 64 RAM4K9 RADDR8 ADDRA11 DOUTA8 RADDR7 DOUTA7 ADDRA10 ADDRA0 DOUTA0 RADDR0 DINA8 DINA7 RW1 DINA0 RW0 WIDTHA1 WIDTHA0 PIPE PIPEA WMODEA BLKA ...
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Timing Waveforms t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-24 • RAM Read for Pass-Through Output t CKH CLK ADD 0 t ...
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IGLOO PLUS DC and Switching Characteristics t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-26 • RAM Write, Output Retained (WMODE = 0) CLK ...
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CLK1 ADD1 0 WEN_B1 t CKQ1 DO1 D n (pass-through) DO1 D (pipelined CCKH CLK2 ADD2 A D DI2 WEN_B2 Figure 2-28 • Write Access after Read onto Same Address t CKH CLK ...
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IGLOO PLUS DC and Switching Characteristics Timing Characteristics 1 Core Voltage Table 2-92 • RAM4K9 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B ...
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Table 2-93 • RAM512X18 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) setup time DS t Input data ...
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IGLOO PLUS DC and Switching Characteristics 1 Core Voltage Table 2-94 • RAM4K9 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ...
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Table 2-95 • RAM512X18 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) setup time DS t Input data ...
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IGLOO PLUS DC and Switching Characteristics FIFO Figure 2-30 • FIFO Model 2- 72 FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 RD0 WW0 ESTOP FULL FSTOP AFULL EMPTY AEVAL11 AEMPTY AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 ...
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Timing Waveforms RCLK/ WCLK RESET_B t RSTFG EMPTY AEMPTY t RSTFG FULL AFULL WA/RA (Address Counter) Figure 2-31 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-32 • FIFO EMPTY Flag and AEMPTY Flag Assertion t ...
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IGLOO PLUS DC and Switching Characteristics WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-33 • FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA MATCH NO MATCH (Address Counter) (EMPTY) 1st Rising Edge After 1st Write RCLK EMPTY ...
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Timing Characteristics 1 Core Voltage Table 2-96 • FIFO Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t Input ...
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IGLOO PLUS DC and Switching Characteristics 1 Core Voltage Table 2-97 • FIFO Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold ...
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Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-36 • Timing Diagram Timing Characteristics 1 Core Voltage Table 2-98 • Embedded FlashROM Access Time Worst Commercial-Case Conditions: T Parameter t Address Setup Time ...
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IGLOO PLUS DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the Characteristics" ...
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... Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. ...
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... Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. Pin information is in the "Pin Descriptions" chapter of the IGLOO PLUS Low Power Flash FPGAs 128-Pin VQFP IGLOO PLUS FPGA Fabric User’s Guide ...
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Package Pin Assignments 128-Pin VQFP AGLP030 Pin Number Function 1 IO119RSB3 2 IO118RSB3 3 IO117RSB3 4 IO115RSB3 5 IO116RSB3 6 IO113RSB3 7 IO114RSB3 8 GND 9 VCCIB3 10 IO112RSB3 11 IO111RSB3 12 IO110RSB3 13 IO109RSB3 14 GEC0/IO108RSB3 15 GEA0/IO107RSB3 16 ...
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VQFP AGLP030 Pin Number Function 106 IO26RSB0 107 IO25RSB0 108 IO23RSB0 109 IO22RSB0 110 IO21RSB0 111 IO19RSB0 112 IO18RSB0 113 VCC 114 IO17RSB0 115 IO16RSB0 116 IO14RSB0 117 IO13RSB0 118 IO12RSB0 119 IO10RSB0 120 IO09RSB0 121 VCCIB0 122 GND ...
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... Package Pin Assignments 176-Pin VQFP 176 1 Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx 176-Pin VQFP R ev isio ...
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VQFP AGLP060 Pin Number Function 1 GAA2/IO156RSB3 2 IO155RSB3 3 GAB2/IO154RSB3 4 IO153RSB3 5 GAC2/IO152RSB3 6 GND 7 VCCIB3 8 IO149RSB3 9 IO147RSB3 10 IO145RSB3 11 IO144RSB3 12 IO143RSB3 13 VCC 14 IO141RSB3 15 GFC1/IO140RSB3 16 GFB1/IO138RSB3 17 GFB0/IO137RSB3 ...
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Package Pin Assignments 176-Pin VQFP AGLP060 Pin Number Function 105 IO62RSB1 106 IO61RSB1 107 GCC2/IO60RSB1 108 GCB2/IO59RSB1 109 GCA2/IO58RSB1 110 GCA0/IO57RSB1 111 GCA1/IO56RSB1 112 VCCIB1 113 GND 114 GCB0/IO55RSB1 115 GCB1/IO54RSB1 116 GCC0/IO53RSB1 117 GCC1/IO52RSB1 118 IO51RSB1 119 IO50RSB1 120 ...
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... CSP Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. IGLOO PLUS Low Power Flash FPGAs ...
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Package Pin Assignments 201-Pin CSP AGLP030 Pin Number Function IO04RSB0 A3 IO06RSB0 A4 IO09RSB0 A5 IO11RSB0 A6 IO13RSB0 A7 IO17RSB0 A8 IO18RSB0 A9 IO24RSB0 A10 IO26RSB0 A11 IO27RSB0 A12 IO31RSB0 A13 NC A14 NC A15 NC B1 ...
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CSP AGLP030 Pin Number Function H14 IO45RSB1 H15 IO43RSB1 J1 GEA0/IO107RSB3 J2 IO105RSB3 J3 IO104RSB3 J4 IO102RSB3 J6 VCCIB3 J7 GND J8 VCC J9 GND J10 VCCIB1 J12 NC J13 NC J14 IO52RSB1 J15 IO50RSB1 K1 IO103RSB3 K2 IO101RSB3 ...
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Package Pin Assignments 201-Pin CSP AGLP060 Pin Number Function A1 IO150RSB3 A2 GAA0/IO00RSB0 A3 GAC0/IO04RSB0 A4 IO08RSB0 A5 IO11RSB0 A6 IO15RSB0 A7 IO17RSB0 A8 IO18RSB0 A9 IO22RSB0 A10 IO26RSB0 A11 IO29RSB0 A12 GBC1/IO31RSB0 A13 GBA2/IO36RSB1 A14 IO41RSB1 A15 NC B1 ...
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CSP AGLP060 Pin Number Function H14 IO64RSB1 H15 IO62RSB1 J1 GFA2/IO134RSB3 J2 GFA0/IO135RSB3 J3 GFB2/IO133RSB3 J4 IO131RSB3 J6 VCCIB3 J7 GND J8 VCC J9 GND J10 VCCIB1 J12 IO61RSB1 J13 IO63RSB1 J14 IO68RSB1 J15 IO66RSB1 K1 IO130RSB3 K2 GFC2/IO132RSB3 ...
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... Package Pin Assignments 281-Pin CSP Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx sio ...
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CSP Pin Number AGLP125 Function A1 GND A2 GAB0/IO02RSB0 A3 GAC1/IO05RSB0 A4 IO09RSB0 A5 IO13RSB0 A6 IO15RSB0 A7 IO18RSB0 A8 IO23RSB0 A9 IO25RSB0 A10 VCCIB0 A11 IO33RSB0 A12 IO41RSB0 A13 IO43RSB0 A14 IO46RSB0 A15 IO55RSB0 A16 IO56RSB0 A17 GBC1/IO58RSB0 ...
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Package Pin Assignments 281-Pin CSP Pin Number AGLP125 Function H8 VCC H9 VCCIB0 H10 VCC H11 VCCIB0 H12 VCC H13 VCCIB1 H15 IO77RSB1 H16 GCB0/IO82RSB1 H18 GCA1/IO83RSB1 H19 GCA2/IO85RSB1 J1 VCOMPLF J2 GFA0/IO189RSB3 J4 VCCPLF J5 GFC0/IO193RSB3 J7 GFA2/IO188RSB3 J8 ...
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CSP Pin Number AGLP125 Function R15 IO109RSB2 R16 GDA1/IO103RSB1 R18 GDB0/IO102RSB1 R19 GDC0/IO100RSB1 T1 IO171RSB3 T2 GEC0/IO169RSB3 T4 GEB0/IO167RSB3 T5 IO157RSB2 T6 IO158RSB2 T7 IO148RSB2 T8 IO145RSB2 T9 IO143RSB2 T10 GND T11 IO129RSB2 T12 IO126RSB2 T13 IO125RSB2 T14 IO116RSB2 ...
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... Package Pin Assignments 289-Pin CSP Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx Ball Pad Corner sio ...
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CSP AGLP030 Pin Number Function A1 IO03RSB0 GND A5 IO10RSB0 A6 IO14RSB0 A7 IO16RSB0 A8 IO18RSB0 A9 GND A10 IO23RSB0 A11 IO27RSB0 A12 NC A13 NC A14 GND A15 NC A16 NC A17 IO30RSB0 ...
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Package Pin Assignments 289-Pin CSP AGLP030 Pin Number Function G10 GND G11 GND G12 IO40RSB1 G13 NC G14 IO39RSB1 G15 IO44RSB1 G16 NC G17 GND GEC0/IO108RSB3 IO112RSB3 IO109RSB3 H7 GND H8 ...
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CSP AGLP030 Pin Number Function GND IO87RSB2 P7 IO80RSB2 P8 GND P9 IO72RSB2 P10 IO67RSB2 P11 IO61RSB2 P12 NC P13 VCCIB2 P14 NC P15 IO60RSB2 P16 IO62RSB2 P17 VJTAG R1 GND ...
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Package Pin Assignments 289-Pin CSP Pin Number AGLP060 Function A1 GAB1/IO03RSB0 GND A5 IO10RSB0 A6 IO14RSB0 A7 IO16RSB0 A8 IO18RSB0 A9 GND A10 IO23RSB0 A11 IO27RSB0 A12 NC A13 NC A14 GND A15 NC A16 ...
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CSP Pin Number AGLP060 Function G13 IO41RSB1 G14 IO47RSB1 G15 IO49RSB1 G16 IO50RSB1 G17 GND H1 VCOMPLF H2 GFB0/IO137RSB3 IO141RSB3 H5 IO143RSB3 H6 GFB1/IO138RSB3 H7 GND H8 GND H9 GND H10 GND H11 GND H12 GCC1/IO52RSB1 ...
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Package Pin Assignments 289-Pin CSP Pin Number AGLP060 Function P8 GND P9 IO91RSB2 P10 IO86RSB2 P11 IO81RSB2 P12 NC P13 VCCIB2 P14 NC P15 GDA2/IO78RSB2 P16 GDC2/IO80RSB2 P17 VJTAG R1 GND R2 GEA2/IO110RSB2 ...
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CSP Pin Number AGLP125 Function A1 GAB1/IO03RSB0 A2 IO11RSB0 A3 IO08RSB0 A4 GND A5 IO19RSB0 A6 IO24RSB0 A7 IO26RSB0 A8 IO30RSB0 A9 GND A10 IO35RSB0 A11 IO38RSB0 A12 IO40RSB0 A13 IO42RSB0 A14 GND A15 IO48RSB0 A16 IO54RSB0 A17 GBC0/IO57RSB0 ...
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Package Pin Assignments 289-Pin CSP Pin Number AGLP125 Function G13 IO64RSB1 G14 IO69RSB1 G15 IO78RSB1 G16 IO76RSB1 G17 GND H1 VCOMPLF H2 GFB0/IO191RSB3 H3 IO195RSB3 H4 IO197RSB3 H5 IO199RSB3 H6 GFB1/IO192RSB3 H7 GND H8 GND H9 GND H10 GND H11 ...
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CSP Pin Number AGLP125 Function P8 GND P9 IO132RSB2 P10 IO125RSB2 P11 IO126RSB2 P12 IO112RSB2 P13 VCCIB2 P14 IO108RSB2 P15 GDA2/IO105RSB2 P16 GDC2/IO107RSB2 P17 VJTAG R1 GND R2 GEA2/IO164RSB2 R3 IO158RSB2 R4 IO155RSB2 R5 IO150RSB2 R6 VCCIB2 R7 IO145RSB2 ...
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Datasheet Information List of Changes The following table lists critical changes that were made in each revision of the IGLOO PLUS datasheet. Revision Revision 11 (Jun 2009) The versioning system for datasheets has been changed. Datasheets are assigned ...
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Datasheet Information Revision Revision 11 (continued) The values in the following tables were updated. 3.3 V LVCMOS and 1.2 V LVCMOS wide range were added to the tables where applicable. Table 2-13 • Summary of I/O Input Buffer Power (per ...
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Revision Revision 11 (continued) The following tables were updated in the section: Table 2-85 • AGLP060 Global Resource Table 2-86 • AGLP125 Global Resource Table 2-88 • AGLP060 Global Resource Table 2-90 • IGLOO PLUS CCC/PLL Specification CCC/PLL Specification maximum ...
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... Datasheet Information Revision Revision 4 (Jul 2008 result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change Product Brief v1.1 1 and Switching Characteristics Advance v0.3 Revision 3 (Jun 2008) Tables have been updated to reflect default values in the software. The default I/O capacitance ...
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Revision Revision 3 (continued) The "289-Pin CSP" CS281 mechanical drawing and not the CS289 mechanical drawing. This has now been corrected. Revision 2 (Jun 2008) The "289-Pin CSP" Packaging v1.2 Revision 1 (Jun 2008) The "289-Pin CSP" Packaging v1.1 The ...
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... Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. ...
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... Fax +44 (0) 1276 607 540 © Actel Corporation. All rights reserved. Actel, Actel Fusion, IGLOO, Libero, Pigeon Point, ProASIC, SmartFusion and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. Actel Japan ...