AGLP060V5-CSG289 Actel, AGLP060V5-CSG289 Datasheet - Page 82

• Manufacturer Part Number: AGLP060V5-CSG289
• Description: FPGA - Field Programmable Gate Array 60K System Gates
• Manufacturer: Actel

Specifications of AGLP060V5-CSG289

• Processor Series: AGLP060
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 60 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO PLUS DC and Switching Characteristics
Table 2-92 • RAM4K9
2- 68
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
AS
AH
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
C2CWWL
C2CRWH
C2CWRH
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Timing Characteristics
1.5 V DC Core Voltage
Address setup time
Address hold time
REN_B, WEN_B setup time
REN_B, WEN_B hold time
BLK_B setup time
BLK_B hold time
Input data (DI) setup time
Input data (DI) hold time
Clock High to new data valid on DO (output retained, WMODE = 0)
Clock High to new data valid on DO (flow-through, WMODE = 1)
Clock High to new data valid on DO (pipelined)
Address collision clk-to-clk delay for reliable write after write on same address – applicable
to closing edge
Address collision clk-to-clk delay for reliable read access after write on same address –
applicable to opening edge
Address collision clk-to-clk delay for reliable write access after read on same address –
applicable to opening edge
RESET_B Low to data out Low on DO (flow-through)
RESET_B Low to data out Low on DO (pipelined)
RESET_B removal
RESET_B recovery
RESET_B minimum pulse width
Clock cycle time
Maximum frequency
J
= 70°C, Worst-Case VCC = 1.425 V
Description
R ev i sio n 1 1
Table 2-6 on page 2-6
for derating values.
0.69
0.13
0.68
0.13
1.37
0.13
0.59
0.30
2.94
2.55
1.51
0.29
0.24
0.40
1.72
1.72
0.51
2.68
0.68
6.24
Std. Units
160
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns