AGL1000V5-FGG256 Actel, AGL1000V5-FGG256 Datasheet - Page 118

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AGL1000V5-FGG256

Manufacturer Part Number
AGL1000V5-FGG256
Description
FPGA - Field Programmable Gate Array 1M System Gates IGLOO
Manufacturer
Actel
Datasheet

Specifications of AGL1000V5-FGG256

Processor Series
AGL1000
Core
IP Core
Maximum Operating Frequency
892.86 MHz
Number Of Programmable I/os
177
Data Ram Size
147456
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
1 M
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AGL1000V5-FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGL1000V5-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
AGL1000V5-FGG256I
Manufacturer:
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IGLOO DC and Switching Characteristics
Figure 2-28 • Timing Model and Waveforms
Table 2-170 • Register Delays
2- 10 4
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
CLKQ
SUD
HD
SUE
HE
CLR2Q
PRE2Q
REMCLR
RECCLR
REMPRE
RECPRE
WCLR
WPRE
CKMPWH
CKMPWL
CLK
Data
EN
Out
PRE
CLR
For specific junction temperature and voltage supply levels, refer to
Timing Characteristics
1.5 V DC Core Voltage
Commercial-Case Conditions: T
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
50%
50%
t
SUE
t
HE
50%
t
CLKQ
50%
t
SUD
0
t
HD
t
PRE2Q
50%
50%
50%
t
J
WPRE
= 70°C, Worst-Case VCC = 1.425 V
50%
Description
50%
50%
t
t
RECPRE
R ev isio n 1 8
WCLR
50%
t
50%
50%
CLR2Q
50%
t
RECCLR
Table 2-6 on page 2-7
50%
t
CKMPWH
t
50%
REMPRE
t
for derating values.
CKMPWL
50%
0.89
0.81
0.00
0.73
0.00
0.60
0.62
0.00
0.24
0.00
0.23
0.30
0.30
0.56
0.56
Std.
50%
50%
t
REMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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