AGL1000V5-FGG256 Actel, AGL1000V5-FGG256 Datasheet - Page 65

• Manufacturer Part Number: AGL1000V5-FGG256
• Description: FPGA - Field Programmable Gate Array 1M System Gates IGLOO
• Manufacturer: Actel

Specifications of AGL1000V5-FGG256

• Processor Series: AGL1000
• Core: IP Core
• Maximum Operating Frequency: 892.86 MHz
• Number Of Programmable I/os: 177
• Data Ram Size: 147456
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 1 M
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-68 •
Table 2-69 •
Drive
Strength
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
2. For specific junction temperature and voltage supply levels, refer to
Drive
Strength
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
2. For specific junction temperature and voltage supply levels, refer to
3. Software default selection highlighted in gray.
equivalent software default drive strength. These values are for normal ranges only.
equivalent software default drive strength. These values are for normal ranges only.
Equivalent
Equivalent
Software
Software
Commercial-Case Conditions: T
Applicable to Standard Plus Banks
Strength
Commercial-Case Conditions: T
Applicable to Standard Plus Banks
Strength
Option
Option
3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage
3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage
Default
Default
12 mA
16 mA
12 mA
16 mA
Drive
4 mA
6 mA
8 mA
Drive
4 mA
6 mA
8 mA
1
1
Speed
Grade t
Speed
Grade t
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
Std.
DOUT
0.97
0.97
0.97
0.97
0.97
DOUT
0.97
0.97
0.97
0.97
0.97
5.84 0.18 1.20
4.76 0.18 1.20
4.76 0.18 1.20
4.02 0.18 1.20
4.02 0.18 1.20
3.33
2.75
2.75
2.45
2.45
t
t
DP
DP
J
J
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
t
0.18 1.20
0.18 1.20
0.18 1.20
0.18 1.20
0.18 1.20
t
DIN
DIN
t
R ev i si o n 1 8
t
PY
PY
t
t
0.66
0.66
0.66
0.66
0.66
EOUT
0.66
0.66
0.66
0.66
0.66
EOUT
Table 2-6 on page 2-7
Table 2-6 on page 2-7
5.86 5.04 2.74 2.71 9.46 8.64
4.78 4.33 3.09 3.33 8.37 7.93
4.78 4.33 3.09 3.33 8.37 7.93
4.04 3.78 3.33 3.73 7.64 7.37
4.04 3.78 3.33 3.73 7.64 7.37
3.35 2.68 2.73
2.77 2.17 3.08
2.77 2.17 3.08
2.47 1.92 3.33
2.47 1.92 3.33
t
t
ZL
ZL
t
t
ZH
ZH
t
t
LZ
LZ
IGLOO Low Power Flash FPGAs
for derating values.
for derating values.
2.88
3.50
3.50
3.90
3.90
t
t
HZ
HZ
6.94
6.36
6.36
6.06
6.06
t
t
ZLS
ZLS
t
6.27
5.77
5.77
5.51
5.51
t
ZHS
ZHS
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 51