A3P125-TQG144 Actel, A3P125-TQG144 Datasheet - Page 55

• Manufacturer Part Number: A3P125-TQG144
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of A3P125-TQG144

• Processor Series: A3P125
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 125 K
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS HIgh Slew
Drive
Strength
100 µA
100 µA
100 µA
100 µA
100 µA
100 µA
Notes:
1. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT
2. Software default selection highlighted in gray.
3. For specific junction temperature and voltage supply levels, refer to
operate at the equivalent software default drive strength. These values are for normal ranges ONLY.
Commercial-Case Conditions: T
Applicable to Advanced I/O Banks
Software
Timing Characteristics
Strength
Option
Default
Equiv.
12 mA
24 mA
16 mA
Drive
4 mA
8 mA
6 mA
1
Speed
Grade
Std.
Std.
Std.
Std.
Std.
Std.
–1
–2
–1
–2
–1
–2
–1
–2
–1
–2
–1
–2
t
DOUT
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
0.60
0.51
0.45
10.07 0.04 0.86 0.36 10.07 8.51 3.48 3.44 12.96 11.40
11.84 0.04 1.02 0.43
8.84
7.59
6.45
5.67
7.59
6.45
5.67
5.46
4.65
4.08
5.15
4.38
3.85
4.75
4.04
3.55
t
DP
J
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
0.03 0.76 0.32
0.04 1.02 0.43
0.04 0.86 0.36
0.03 0.76 0.32
0.04 1.02 0.43
0.04 0.86 0.36
0.03 0.76 0.32
0.04 1.02 0.43
0.04 0.86 0.36
0.03 0.76 0.32
0.04 1.02 0.43
0.04 0.86 0.36
0.03 0.76 0.32
0.04 1.02 0.43
0.04 0.86 0.36
0.03 0.76 0.32
t
DIN
t
R e v i s i o n 9
PY
t
EOUT
Table 2-6 on page 2-6
11.84 10.00 4.10 4.04 15.23 13.40
8.84
7.59
6.45
5.67
7.59
6.45
5.67
5.46
4.65
4.08
5.15
4.38
3.85
4.75
4.04
3.55
t
ZL
7.47 3.06 3.02 11.38 10.00
6.18 4.62 4.95 10.98 9.57
5.25 3.93 4.21 9.34
4.61 3.45 3.70 8.20
6.18 4.62 4.95 10.98 9.57
5.25 3.93 4.21 9.34
4.61 3.45 3.70 8.20
4.29 4.97 5.54 8.86
3.65 4.22 4.71 7.53
3.20 3.71 4.14 6.61
3.89 5.04 5.69 8.55
3.31 4.29 4.84 7.27
2.91 3.77 4.25 6.38
3.22 5.14 6.28 8.15
2.74 4.37 5.34 6.93
2.40 3.84 4.69 6.09
t
ZH
t
LZ
for derating values.
ProASIC3 Flash Family FPGAs
t
HZ
t
ZLS
t
8.14
7.15
8.14
7.15
7.68
6.54
5.74
7.29
6.20
5.44
6.61
5.62
4.94
ZHS
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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