AGLN020V2-CSG81 Actel, AGLN020V2-CSG81 Datasheet - Page 70

• Manufacturer Part Number: AGLN020V2-CSG81
• Description: FPGA - Field Programmable Gate Array 20K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN020V2-CSG81

• Processor Series: AGLN020
• Core: IP Core
• Number Of Macrocells: 172
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 52
• Supply Voltage (max): 1.5 V
• Supply Current: 6 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 20 K
• Package / Case: CSP-81
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO nano DC and Switching Characteristics
Table 2-84 • Output DDR Propagation Delays
2- 56
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDROCLKQ
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
DDOMAX
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
1.2 V DC Core Voltage
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
J
= 70°C, Worst-Case VCC = 1.14 V
Description
R ev i sio n 1 1
Table 2-7 on page 2-7
for derating values.
160.00
1.60
1.09
1.16
0.00
0.00
1.99
0.00
0.24
0.19
0.31
0.28
Std.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns