A42MX24-PLG84 Actel, A42MX24-PLG84 Datasheet - Page 54

• Manufacturer Part Number: A42MX24-PLG84
• Description: FPGA - Field Programmable Gate Array 36K System Gates
• Manufacturer: Actel

Specifications of A42MX24-PLG84

• Processor Series: A42MX24
• Core: IP Core
• Number Of Macrocells: 912
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 140
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 36 K
• Package / Case: PLCC-84
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 32 •
1 -4 8
Parameter Description
Logic Module Propagation Delays
t
t
t
t
Logic Module Predicted Routing Delays
t
t
t
t
t
Logic Module Sequential Timing
t
t
t
t
t
t
t
t
t
t
t
f
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
PD1
CO
GO
RS
RD1
RD2
RD3
RD4
RD8
SUD
HD
SUENA
HENA
WCLKA
WASYN
A
INH
INSU
OUTH
OUTSU
MAX
40MX and 42MX FPGA Families
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer utility.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
A42MX09 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
Single Module
Sequential Clock-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Flip-Flop (Latch) Data Input Set-Up
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active
Pulse Width
Flip-Flop (Latch) Asynchronous
Pulse Width
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Set-Up
Output Buffer Latch Hold
Output Buffer Latch Set-Up
Flip-Flop (Latch) Clock Frequency
PD1
+ t
3, 4
1
RD1
+ t
2
PDn
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
‘–3’ Speed
0.3
0.0
0.4
0.0
3.4
4.5
3.5
0.0
0.3
0.0
0.3
, t
CO
CCA
+ t
268
1.2
1.3
1.2
1.2
0.7
0.9
1.2
1.4
2.3
RD1
= 4.75V, T
+ t
v6.1
‘–2’ Speed
PDn
0.4
0.0
0.5
0.0
3.8
4.9
3.8
0.0
0.3
0.0
0.3
, or t
J
= 70°C)
244
PD1
1.3
1.4
1.4
1.6
0.8
1.0
1.3
1.5
2.6
+ t
RD1
‘–1’ Speed
0.4
0.0
0.5
0.0
4.3
5.6
4.3
0.0
0.4
0.0
0.4
+ t
SUD
224
1.5
1.6
1.6
1.8
0.9
1.2
1.5
1.7
2.9
, whichever is appropriate.
‘Std’ Speed
0.5
0.0
0.6
0.0
5.0
6.6
5.1
0.0
0.4
0.0
0.4
195
1.8
1.9
1.8
2.1
1.0
1.4
1.7
2.0
3.4
‘–F’ Speed
0.6
0.7
0.0
0.8
0.0
7.0
9.2
7.1
0.0
0.6
0.0
117
2.5
2.7
2.6
2.9
1.4
1.9
2.4
2.9
4.8
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns