APA300-PQ208I Actel, APA300-PQ208I Datasheet - Page 139

• Manufacturer Part Number: APA300-PQ208I
• Description: FPGA - Field Programmable Gate Array 300K System Gates
• Manufacturer: Actel

Specifications of APA300-PQ208I

• Processor Series: APA300
• Core: IP Core
• Maximum Operating Frequency: 5 MHz
• Number Of Programmable I/os: 158
• Data Ram Size: 73728
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 300 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Number
N20
Pin
P10
P11
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N21
N22
N23
N24
N25
N26
P1
P2
P3
P4
P5
P6
P7
P8
P9
N4
N5
N6
N7
N8
N9
676-Pin FBGA
Function
APA600
I/O / GL3
I/O / GL4
I/O / GL2
PPECL1 /
NPECL1
NPECL2
AVDD
Input
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
GND
GND
V
V
V
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DD
DD
DD
Function
APA750
I/O / GL3
I/O / GL4
I/O / GL2
PPECL1 /
NPECL1
NPECL2
AVDD
Input
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
GND
GND
V
V
V
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DD
DD
DD
Number
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
Pin
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
R1
R2
R3
R4
R5
R6
R7
R8
R9
676-Pin FBGA
I/O / GLMX2 I/O / GLMX2
Function
APA600
PPECL2 /
AGND
AVDD
Input
GND
GND
GND
GND
GND
GND
V
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
V
v5.9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
DDP
DDP
DDP
DD
DD
DD
Function
APA750
PPECL2 /
AGND
AVDD
Input
GND
GND
GND
GND
GND
GND
V
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
V
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DDP
DD
DD
DD
Number
Pin
R20
R21
R22
R23
R24
R25
R26
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
U1
U2
T1
T2
T3
T4
T5
T6
T7
T8
T9
ProASIC
676-Pin FBGA
PLUS
Function
APA600
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
Flash Family FPGAs
DD
DD
Function
APA750
V
GND
GND
GND
GND
GND
GND
GND
GND
V
V
V
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DDP
DDP
DD
DD
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