APA300-PQ208I Actel, APA300-PQ208I Datasheet - Page 51

• Manufacturer Part Number: APA300-PQ208I
• Description: FPGA - Field Programmable Gate Array 300K System Gates
• Manufacturer: Actel

Specifications of APA300-PQ208I

• Processor Series: APA300
• Core: IP Core
• Maximum Operating Frequency: 5 MHz
• Number Of Programmable I/os: 158
• Data Ram Size: 73728
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 300 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-26 • AC Specifications (3.3 V PCI Revision 2.2 Operation)
Symbol Parameter
I
I
I
I
slew
slew
Note: * Refer to the PCI Specification document rev. 2.2.
OH(AC)
OL(AC)
CL
CH
R
F
Switching Current High
(Test Point)
Switching Current Low
(Test Point)
Low Clamp Current
High Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
Condition
0.3V
0.7V
V
V
0.6V
0.18V
V
V
0.2V
0 < V
–3 < V
0.6V
OUT
DDP
OUT
DDP
Pad Loading Applicable to the Rising Edge PCI
Pad Loading Applicable to the Falling Edge PCI
Output
Buffer
Output
Buffer
DDP
DDP
DDP
DDP
DDP
OUT
= 0.7V
> V
= 0.18V
+ 4 > V
DDP
IN
≤ V
< V
> V
to 0.6V
to 0.2V
OUT
≤ –1
≤ 0.3V
> V
OUT
OUT
Pin
Pin
OUT
DDP
IN
1kΩ
≥ 0.6V
OUT
DDP
≥ V
*
DDP
DDP
DDP
< 0.9V
< V
> 0.1V
> 0
DDP
*
DDP
DDP
load
load
10 pF
*
+ 1
DDP
DDP
*
*
1/2 in. maxx
*
*
*
1
v5.9
10 pF
25 + (V
1kΩ
(–17.1 + (V
Commercial/Industrial/Military/MIL-STD- 883
–25 + (V
IN
(26.7V
–12V
– V
16V
Min.
IN
DDP
1
1
DDP
+ 1)/0.015
DDP
DDP
OUT
– 1)/0.015
– V
)
OUT
))
See equation C – page 124 of
See equation D – page 124 of
ProASIC
the PCI Specification
the PCI Specification
document rev. 2.2
document rev. 2.2
–32V
38V
PLUS
Max.
4
4
DDP
DDP
Flash Family FPGAs
Units
V/ns
V/ns
mA
mA
mA
mA
mA
mA
mA
mA
2-41