A40MX02-PLG68 Actel, A40MX02-PLG68 Datasheet - Page 53

• Manufacturer Part Number: A40MX02-PLG68
• Description: FPGA - Field Programmable Gate Array 3K System Gates
• Manufacturer: Actel

Specifications of A40MX02-PLG68

• Processor Series: A40MX02
• Core: IP Core
• Number Of Macrocells: 295
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 57
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 3000
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 31 •
Parameter Description
CMOS Output Module Timing
t
t
t
t
t
t
d
d
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
4. Delays based on 35 pF loading.
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
TLH
THL
device performance. Post-route timing analysis or simulation is required to determine actual performance.
time for this macro.
A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
Delta LOW to HIGH
Delta HIGH to LOW
4
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
‘–3’ Speed
CC
0.03
11.1
0.05
5.5
4.8
4.7
6.8
8.2
= 3.0V, T
v6.1
‘–2’ Speed
J
= 70°C)
0.05
0.03
12.8
5.5
7.9
9.5
6.4
5.5
‘–1’ Speed
14.5
10.7
0.06
0.04
7.2
6.2
6.2
8.9
‘Std’ Speed
40MX and 42MX FPGA Families
10.5
17.1
12.6
0.07
0.04
8.5
7.3
7.3
‘–F’ Speed
11.9
10.2
10.2
14.7
23.9
17.7
0.10
0.06
Units
ns/pF
ns/pF
ns
ns
ns
ns
ns
ns
1-47