APA300-FGG144 Actel, APA300-FGG144 Datasheet - Page 175

• Manufacturer Part Number: APA300-FGG144
• Description: FPGA - Field Programmable Gate Array 300K System Gates
• Manufacturer: Actel

Specifications of APA300-FGG144

• Processor Series: APA300
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 290
• Data Ram Size: 73728
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 300 K
• Package / Case: FPBGA-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Previous version
Advance v0.6
(continued)
Advance v0.5
Advance v0.4
Advance v0.3
The
The
The
The "Nominal Supply Voltages’ section was updated.
The
The
The
Military Temperature and MIL-STD-883B Temperature Only" section
The
The
The
The
The
The
The
The description for the V
The
Figure 2-9 • ProASICPLUS JTAG Boundary Scan Test Logic Circuit
Controller State Diagram
The
The
The
The
The
The
The
The
The
WDATA has ben changed to DI, and RDATA has been changed to DO to make them consistent
with the signal names found in the Macro Library Guide.
Figure 2-18 • Example SRAM Block Diagrams
have been updated.
The
updated.
The table in the
The
The
The
The
The
Military Temperature and MIL-STD-883B Temperature Only" section
The
The
Figure 2-11 • PLL Block – Top-Level View and Detailed PLL Block Diagram
Figure 2-10 • TAP Controller State Diagram
Tables 5, 6, and 7 from Advanced v0.3 were removed.
Changes in current version (v5.9)
"Calculating Typical Power Dissipation" section
"Absolute Maximum Ratings*" section
"Programming, Storage, and Operating Limits" section
"Recommended Operating Conditions" section
"DC Electrical Specifications (V
"Synchronous Write and Read to the Same Location" section
"Asynchronous Write and Synchronous Read to the Same Location" section
"Asynchronous FIFO Read" section
"Pin Description" section
"Recommended Design Practice for VPN/VPP" section
"100-Pin TQFP" section
"484-Pin FBGA" section
"Plastic Device Resources" section
"Tristate Buffer Delays" section
"Output Buffer Delays" section
"Input Buffer Delays" section
"Global Input Buffer Delays" section
"456-Pin PBGA" section
"676-Pin FBGA" section
"ProASICPLUS Product Profile" section
"Plastic Device Resources" section
"ProASICPLUS I/O Power Supply Voltages"
"Calculating Typical Power Dissipation" section
"Programming, Storage, and Operating Limits" section
"Nominal Supply Voltages’ section
"DC Electrical Specifications (V
"Recommended Operating Conditions" section
"ProASIC
"DC Electrical Specifications (V
"DC Electrical Specifications (V
"Design Environment" section
PLUS
"Package Thermal Characteristics" section
Clock Management System" section
PN
have been updated.
pin has changed.
is new.
is new.
has been updated.
has been updated.
has been updated.
has been updated.
DDP
DDP
DDP
has been updated.
DDP
has been updated.
and
has been updated.
has been updated.
= 2.5 V ±0.2V)" section
= 2.5 V ±0.2V)" section
has been updated.
was updated.
= 3.3 V ±0.3 V and V
= 3.3 V ±0.3 V and V
has been updated.
has been changed.
was updated.
Figure 2-23 • Tristate Buffer Delays
v5.9
is new.
sectionhas been updated.
and
was updated.
is new.
was updated.
was updated.
Figure 2-19 • Basic FIFO Block Diagrams
was updated.
is new.
has been updated.
was updated.
is new.
DD
DD
was updated.
was updated.
was updated.
= 2.5 V ±0.2 V) Applies to
= 2.5 V ±0.2 V) Applies to
was updated.
was updated.
and
was updated.
Figure 2-10 • TAP
ProASIC
was updated.
have been
PLUS
Flash Family FPGAs
and
and
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