APA300-FGG144 Actel, APA300-FGG144 Datasheet - Page 29
APA300-FGG144
Manufacturer Part Number
APA300-FGG144
Description
FPGA - Field Programmable Gate Array 300K System Gates
Manufacturer
Actel
Datasheet
1.APA075-FGG144.pdf
(178 pages)
Specifications of APA300-FGG144
Processor Series
APA300
Core
IP Core
Maximum Operating Frequency
150 MHz
Number Of Programmable I/os
290
Data Ram Size
73728
Supply Voltage (max)
2.7 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
2.3 V
Number Of Gates
300 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
APA300-FGG144A
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
APA300-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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PLL I/O Constraints
PLL locking is guaranteed only when the following constraints are followed:
Table 2-10 • PLL I/O Constraints
I/O Type
SSO
PLL locking is guaranteed only when using low drive strength and
low slew rate I/O. PLL locking may be inconsistent when using high
drive strength or high slew rate I/Os
APA300
APA600
APA1000
APA300
APA600
APA1000
T
J
≤
v5.9
–40°C
Hermetic packages
Plastic packages
Hermetic packages
Plastic packages
Hermetic packages
Plastic packages
Hermetic packages
Plastic packages
Hermetic packages
Plastic packages
Hermetic packages
Plastic packages
≤
≤
≤
≤
≤
≤
16 SSO
32 SSO
32 SSO
20 SSO
64 SSO
64 SSO
≤
≤
≤
≤
≤
≤
8 SSO
16 SSO
16 SSO
12 SSO
32 SSO
32 SSO
ProASIC
With FIN
outputs
simultaneously
With FIN
outputs switching on positive
clock edge, half switching on
the negative clock edge no less
than 10 ns later
PLUS
Value T
No Constraints
≤
Flash Family FPGAs
≤
50 MHz and half
J
180 MHz and
> –40°C
switching
2-19
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