SI5321-H-BL Silicon Laboratories Inc, SI5321-H-BL Datasheet
SI5321-H-BL
Specifications of SI5321-H-BL
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SI5321-H-BL Summary of contents
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... SONET/SDH line/port cards Terabit routers Description The Si5321 is a precision clock multiplier that exceeds the requirements of high-speed communication systems, including OC-192/OC-48 and 10 Gigabit Ethernet. This device phase locks to an input clock in the 19, 39, 78, 155, 311 or 622 MHz frequency range and generates a frequency-multiplied clock output that can be configured for operation in the 19, 39, 78, 155, 622, 1244, or 2488 MHz frequency range. Silicon Laboratories ® ...
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... Si5321 2 Rev. 2.5 ...
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... Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3. Pin Descriptions: Si5321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6. 9x9 mm PBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Rev ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5321 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient temperature of –20 to 85° C. ...
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... C LKIN + C LKIN – peration with Single-Ended C lock Input* N ote: W hen using single-ended clock sources, the unused clock input on the Si5321 m ust be ac-coupled to ground. C LKIN + C LKIN – (C LKIN+) – (C LKIN – peration with D ifferential C lock Input N ote: Transm ission line term ination, when required, m ust be provided Figure 1 ...
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... Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac- coupled to ground. 3. Transmission line termination, when required, must be provided externally. 4. Although the Si5321 device can operate with input clock swings as high as 1500 mV maintaining the input clock amplitude below 500 ...
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... INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 Note: The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock multiplication function with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/237, 237/255, 66/64, or 64/66 for FEC rate conversion. ...
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... Output Clock Duty Cycle C RSTN/CAL Pulse Width Note: The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock multiplication function with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/237, 237/255, 66/64, or 64/66 for FEC rate conversion. ...
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... LOS Condition VALTIME = 0 VALTIME = 1 Note: The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock multiplication function with an option for additional frequency scaling by a factor of 255/238, 238/255, 255/237, 237/255, 66/64, or 64/66 for FEC rate conversion. Symbol ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/μs unit is used here since the maximum phase transient magnitude for the Si5321 (tPT_MTIE) never reaches one nanosecond. 10 Symbol ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/μs unit is used here since the maximum phase transient magnitude for the Si5321 (tPT_MTIE) never reaches one nanosecond. Symbol Test Condition ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/μs unit is used here since the maximum phase transient magnitude for the Si5321 (tPT_MTIE) never reaches one nanosecond. 12 Symbol ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/μs unit is used here since the maximum phase transient magnitude for the Si5321 (tPT_MTIE) never reaches one nanosecond. Symbol Test Condition ...
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... For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/μs unit is used here since the maximum phase transient magnitude for the Si5321 (tPT_MTIE) never reaches one nanosecond. 14 Symbol ...
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... Table 6. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient 0 -20 -40 -60 -80 -100 -120 -140 -160 Figure 4. Typical Si5321 Phase Noise (CLKIN = 155.52 MHz, CLKOUT = 622.08 MHz, and Symbol Value V –0.5 to 3.6 DD33 V –0 DIG T –55 to 150 JCT T –55 to 150 STG Symbol Test Condition ϕ ...
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... Input Clock Source 0.1 μF Input Clock Frequency Select FEC Scaling Select PLL Bandwidth Select PLL Bandwidth Multiplier LOS Validation Time Powerdown Control Fixed Delay Mode Control Figure 5. Si5321 Typical Application Circuit (3.3 V Supply) 16 2200 kΩ 1% CLKIN+ CLKIN– INFRQSEL[2:0] Si5321 ...
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... The multiplication factor is configured by selecting the input and output clock frequency ranges for the device. The Si5321 accepts an input clock in the 19, 38, 77, 155, 311, or 622 MHz frequency range. The input frequency range is selected using the INFRQSEL[2:0] pins. The INFRQSEL[2:0] settings and associated output clock rates are listed in Table 8. The Si5321’ ...
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... MHz 6400 2.2.1. FEC Rate Conversion 6400 — The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock frequency 6400 multiplication function with an option for additional 6400 forward or reverse frequency scaling by a factor of 255/ ...
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... LOS condition is declared; the Si5321 goes into digital hold mode, and the LOS output alarm signal is set high. The LOS sampling circuitry runs at a frequency of f ...
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... The frequency accuracy specifications for digital hold mode are given in Table 4 on page 10. 2.6. Hitless Recovery from Digital Hold When the Si5321 device is locked to a valid input clock, a loss of the input clock switches the device to digital hold mode. When the input clock signal returns, the device performs a hitless transition from digital hold mode back to the selected input clock ...
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... V Typically, the resistor is incorporated into the capacitor’s equivalent series resistance (ESR). The target RC time constant for this combination μ s. The capacitor used in the Si5321 evaluation board μ f circuit. For tantalum capacitor with an ESR of 0.8 Ω . This gives an RC time constant of 26.4 μ ...
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... Precision clock circuits are susceptible to board noise and EMI. To take precautions against unacceptable levels of board noise and EMI affecting performance of the Si5321, consider the following: Power the device from 3.3 V since the internal regulator provides > isolation to the V pins (which power the PLL circuitry). ...
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... Pin Descriptions: Si5321 8 7 Rsvd_NC Rsvd_NC Rsvd_NC Rsvd_GND Rsvd_GND GND DH_ACTV VDD25 CAL_ACTV VDD25 LOS VDD25 GND GND FRQSEL[1] CLKOUT– Figure 10. Si5321 Pin Configuration (Bottom View Rsvd_NC Rsvd_NC Rsvd_NC FEC[0] Rsvd_GND Rsvd_NC FXDDELAY FRQSEL[2] GND GND GND GND VDD25 VDD33 ...
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... A FEC[1] B BWSEL[0] FEC[2] C BWSEL[1] VSEL33 D CLKIN+ BWBOOST E CLKIN– GND F INFRQSEL[0] GND G INFRQSEL[1] GND H INFRQSEL[2] REXT Figure 11. Si5321 Pin Configuration (Transparent Top View FEC[0] Rsvd_NC Rsvd_NC Rsvd_NC FRQSEL[2] FXDDELAY Rsvd_NC Rsvd_GND GND GND GND GND VDD33 VDD33 VDD33 VDD25 VDD33 VDD33 ...
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... H1 INFRQSEL[2] H6 CLKOUT+ H7 CLKOUT– *Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a logic low state if the input is not driven from an external source. Table 10. Si5321 Pin Descriptions Signal Level I AC Coupled System Clock Input. ...
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... B3 FRQSEL[2] A3 FEC[0] A2 FEC[1] B2 FEC[2] *Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a logic low state if the input is not driven from an external source. 26 I/O Signal Level I* LVTTL* Clock Output Frequency Range Select. Select the frequency range of the clock output, CLK- OUT ...
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... C1 BWSEL[1] D2 BWBOOST B4 FXDDELAY *Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a logic low state if the input is not driven from an external source. Signal Level I* LVTTL* Bandwidth Select. BWSEL[1:0] pins set the bandwidth of the loop filter within the DSPLL to 6400, 3200, 1600, or 800 Hz as indicated below ...
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... CAL_ACTV C2 VSEL33 D3–D5 DD33 E3–E5 *Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a logic low state if the input is not driven from an external source. 28 I/O Signal Level I* LVTTL* Clock Validation Time for LOS. ...
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... H2 REXT A4–8, B5, B8 RSVD_NC B6, B7, C8 RSVD_GND *Note: The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a logic low state if the input is not driven from an external source. Signal Level 2.5 V Compensation Network. Supply DD These pins provide a means of connecting the compensation network for the on-chip regulator ...
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... Si5321 4. Ordering Guide Part Number Si5321-G-BC Si5321-H-BL Si5321-H-GL 30 Package Temperature Range 63-Ball CBGA – °C (Prior Revision) RoHS-5 63-Ball PBGA – °C (Current Revision) RoHS-5 63-Ball PBGA – °C (Current Revision) RoHS-6 Rev. 2.5 ...
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... Package Outline Figure 12 illustrates the package details for the Si5321. Table 11 lists the values for the dimensions shown in the illustration. Figure 12. 63-Ball Plastic Ball Grid Array (PBGA) Table 11. Package Diagram Dimensions (mm) Symbol Min Nom A 1.24 1.41 A1 0.40 0.50 A2 0.34 0.38 A3 0.50 ...
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... Si5321 6. 9x9 mm PBGA Card Layout Symbol Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad µ ...
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... Updated Figure 12, “63-Ball Plastic Ball Grid Array (PBGA),” on page 31. Updated Table 11, “Package Diagram Dimensions (mm),” on page 31. Added Figure 4, “Typical Si5321 Phase Noise (CLKIN = 155.52 MHz, CLKOUT = 622.08 MHz, and Loop BW = 800 Hz),” on page 15. Revision 2.1 to Revision 2.2 Updated Table 3, “AC Characteristics,” on page 7. ...
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... Si5321 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...