SI5321-H-BL Silicon Laboratories Inc, SI5321-H-BL Datasheet - Page 22

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SI5321-H-BL

Manufacturer Part Number
SI5321-H-BL
Description
IC CLOCK MULT SONET/SDH 63-PBGA
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of SI5321-H-BL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Si5321
2.13. Design and Layout Guidelines
Precision clock circuits are susceptible to board noise
and EMI. To take precautions against unacceptable
levels of board noise and EMI affecting performance of
the Si5321, consider the following:
22
Power the device from 3.3 V since the internal
regulator provides >40 dB of isolation to the V
pins (which power the PLL circuitry).
When powering the device from 3.3 V, use an
isolated, local plane to connect the V
Avoid running signal traces over or below this plane
without a ground plane in between.
Route all I/O traces between ground planes as much
as possible
Maintain an input clock amplitude in the 200 mV
500 mV
Excessive high-frequency harmonics of the input
clock should be minimized. The use of filters on the
input clock signal can be used to remove high-
frequency harmonics.
PP
differential range.
DD25
pins.
DD25
PP
Rev. 2.5
to

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