XR2211ACP-F Exar Corporation, XR2211ACP-F Datasheet - Page 16

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XR2211ACP-F

Manufacturer Part Number
XR2211ACP-F
Description
IC FSK DEMOD/TONE DECOD 14PDIP
Manufacturer
Exar Corporation
Datasheet

Specifications of XR2211ACP-F

Package / Case
14-DIP (0.300", 7.62mm)
Includes
Carrier Detector
Function
FSK Demodulator, Tone Decoder
Voltage - Supply
4.5 V ~ 20 V
Current - Supply
5mA
Power (watts)
900mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Mounting Style
Through Hole
Product
PLL
Supply Voltage
4.5 Volts to 20 Volts
Frequency Range
0.01Hz To 300kHz
Rf Type
Quadrature
Supply Voltage Range
4.5V To 20V
Rf Ic Case Style
DIP
No. Of Pins
14
Operating Temperature Range
0°C To +70°C
Filter Terminals
DIP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Interface
-
Number Of Circuits
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
1016-1309-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR2211ACP-F
Manufacturer:
Exar
Quantity:
490
Company:
Part Number:
XR2211ACP-F
Quantity:
399
Company:
Part Number:
XR2211ACP-F
Quantity:
6
Company:
Part Number:
XR2211ACP-F
Quantity:
335
Design Instructions:
The circuit of Figure 12 can be optimized for any tone detection application by the choice of the 5 key circuit components:
R
(All resistance in
a) Choose value of timing resistor R
b) Calculate value of C
c) Calculate R
Note: The total detection bandwidth covers the frequency range of f
d) Calculate value of C
e) Calculate value of the filter capacitor C
Design Examples:
Tone detector with a detection band of + 100Hz:
a) Choose value of timing resistor R
b) Calculate value of C
XR-2211A
0
, R
current that the internal voltage reference can deliver. The recommended value is R
is normally fine-tuned with the series potentiometer, R
Normally, = 0.5 is recommended.
Increasing C
Increasing C
current that the internal voltage reference can deliver. The recommended value is R
is normally fine-tuned with the series potentiometer, R
Rev. 1.04
1
, C
0
C
R
C
C
C
, C
O
1
1
D
0
1
and C
1
R
1250· C
R
16
R
1
D
to set the bandwidth + f (See design equation 5):
0
R
0
1
0
f
1
improves the out-of-band signal rejection, but increases the PLL capture time.
· f
slows down the logic output response time.
· f
’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
· fs
1
f
0
S
·
·2
D
C in F
2
. For a given input, the tone frequency, f
0
0
1
0
20, 000·1, 000
from design equation (1) or from Figure 7 f
for a given loop damping factor:
from design equation (1) or from Figure 6 f
1
0
0
to be in the range of 10K
to be in the range of 10K
D
50 nF
. To avoid chatter at the logic output, with R
16
X
X
.
.
O
S
, these parameters are calculated as follows:
+ f
to 50K . This choice is dictated by the max./min.
to 50K . This choice is dictated by the max./min.
S
S
= f
= f
O
O
:
:
0
0
= 20 K . The final value of R
= 20K . The final value of R
D
= 470K , C
D
must be:
0
0

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