ADP3212MNR2G ON Semiconductor, ADP3212MNR2G Datasheet - Page 32

• Manufacturer Part Number: ADP3212MNR2G
• Description: IC CTLR BUCK 7BIT 2PHASE 48QFN
• Manufacturer: ON Semiconductor

Specifications of ADP3212MNR2G

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 3.3 V ~ 22 V
• Number Of Outputs: 1
• Voltage - Output: 0.3 V ~ 1.5V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 48-TFQFN Exposed Pad
• Output Voltage: 0.9512 V
• Output Current: 52 A
• Input Voltage: 8 V to 19 V
• Supply Current: 7 mA
• Switching Frequency: 300 KHz
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Set the Initial Transient
Figure 36. Transient Setting Waveform, Load Step
a. Increase the resistance of the ramp resistor
b. For V
c. For V
1. With the dynamic load set at its maximum step
2. If both overshoots are larger than desired, try the
3. For load release (see Figure 37), if V
dynamic loads have an excessive overshoot at
powerup if a minimum current is incorrectly set
(this is an issue if a VTT tool is in use).
size, expand the scope time scale to 2 ms/div to
5 ms/div. This results in a waveform that may have
two overshoots and one minor undershoot before
achieving the final desired value after V
(see Figure 36).
following adjustments in the order shown.
If these adjustments do not change the response, it is
because the system is limited by the output
decoupling. Check the output response and the
switching nodes each time a change is made to
ensure that the output decoupling is stable.
larger than the value specified by IMVP−6.5, a
greater percentage of output capacitance is needed.
Either increase the capacitance directly or decrease
the inductor values. (If inductors are changed,
however, it will be necessary to redesign the
circuit using the information from the spreadsheet
and to repeat all tuning guide procedures).
V
TRAN1
(R
frequency.
by 25%.
RAMP
TRAN2
TRAN1
V
) by 25%.
TRAN2
, increase R
, increase C
V
DROOP
A
B
or increase the switching
by 25% and decrease C
TRANREL
DROOP
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is
A
32
Layout and Component Placement
performance of a switching regulator in a PC system.
General Recommendations
Figure 37. Transient Setting Waveform, Load Release
The following guidelines are recommended for optimal
1. For best results, use a PCB of four or more layers.
2. When high currents must be routed between PCB
3. If critical signal lines (including the output voltage
4. An analog ground plane should be used around
This should provide the needed versatility for
control circuitry interconnections with optimal
placement; power planes for ground, input, and
output; and wide interconnection traces in the rest
of the power delivery current paths. Keep in mind
that each square unit of 1 oz copper trace has a
resistance of ~0.53 mW at room temperature.
layers, vias should be used liberally to create
several parallel current paths so that the resistance
and inductance introduced by these current paths is
minimized and the via current rating is not
exceeded.
sense lines of the APD3212/NCP3218/
NCP3218G) must cross through power circuitry, it
is best if a signal ground plane can be interposed
between those signal lines and the traces of the
power circuitry. This serves as a shield to
minimize noise injection into the signals at the
expense of increasing signal ground noise.
and under the APD3212/NCP3218/NCP3218G for
referencing the components associated with the
controller. This plane should be tied to the nearest
ground of the output decoupling capacitor, but
should not be tied to any other power circuitry to
prevent power currents from flowing into the
plane.
V
TRANREL
V
DROOP