EVB-USB4640 SMSC, EVB-USB4640 Datasheet - Page 19

• Manufacturer Part Number: EVB-USB4640
• Description: EVALUATION BOARD FOR USB4640
• Manufacturer: SMSC

Specifications of EVB-USB4640

• Main Purpose: Interface, USB 2.0 Hub
• Embedded: *
• Utilized Ic / Part: USB4640
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1107

High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller
Datasheet
SMSC USB4640/USB4640i
SPI_SPD_SEL
SPI_CLK /
SPI_CE_n
SYMBOL
SPI_DO /
xD_nWP
GPIO4 /
GPIO5 /
GPIO1 /
SPI_DI
SDA /
LED /
SCL
TXD
48-PIN
QFN
21
10
37
11
8
9
Table 6.1 USB4640/USB4640i Pin Descriptions (continued)
(Table
BUFFER
I/O12PD
O8PD
TYPE
I/O12
I/O12
I/O12
O12
I/O6
I/O6
I/O6
6.2)
DESCRIPTION
xD-Picture Card Write Protect
This pin is an active low write protect signal for the xD-Picture Card
device. This pin has a weak pull-down resistor that is permanently
enabled.
SPI Chip Enable
This is the active low chip enable output. If the SPI interface is
enabled, this pin must be driven high in power down states.
This is the SPI clock out to the serial ROM. See
BOOT Sequence"
drive this pin low.
This pin may be used either as input, edge sensitive interrupt input,
or output. Custom firmware is required to activate this function.
When configured, this is the I
This is the data out for the SPI port. See
Sequence"
This pin may be used either as input, edge sensitive interrupt input,
or output. Custom firmware is required to activate this function.
This pin is the data pin when the device is connected to the optional
I
This pin is used to select the speed of the SPI interface. During
nRESET assertion, this pin will be tri-stated with the weak pull-down
resistor enabled. When nRESET is negated, the value on the pin will
be internally latched, and the pin will revert to SPI_DO functionality,
the internal pull-down will be disabled.
‘0’ = 30 MHz (No external resistor should be applied.)
‘1’ = 60 MHz (A 10 K external pull-up resistor must be applied.)
If the latched value is '1', then the pin is tri-stated when the chip is
in the suspend state.
If the latched value is '0', then the pin is driven low during a suspend
state.
This is the SPI data in to the controller from the ROM. This pin has
a weak internal pull-down applied at all times to prevent floating.
General Purpose I/O
This pin may be used either as input, edge sensitive interrupt input,
or output. Custom firmware is required to activate this function.
GPIO1 can be used as an LED output.
This signal can be configured as the TXD output of the internal
UART. Custom firmware is required to activate this function.
2
C EEPROM.
SPI INTERFACE
DATASHEET
MISC
19
for diagram and usage instructions.
for diagram and usage instructions. During reset,
2
C EEPROM clock pin.
Section 6.4, "ROM BOOT
Section 6.4, "ROM
Revision 1.0 (06-09-09)