EVB-USB4640 SMSC, EVB-USB4640 Datasheet - Page 51

• Manufacturer Part Number: EVB-USB4640
• Description: EVALUATION BOARD FOR USB4640
• Manufacturer: SMSC

Specifications of EVB-USB4640

• Main Purpose: Interface, USB 2.0 Hub
• Embedded: *
• Utilized Ic / Part: USB4640
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1107

High Speed Inter-Chip (HSIC) USB 2.0 Hub and Flash Media Controller
Datasheet
SMSC USB4640/USB4640i
8.4.6.1
8.4.6.2
8.4.7
8.5
8.6
8.6.1
8.6.2
Implementation Characteristics
The device will only access an EEPROM using the sequential read protocol.
Pull-Up Resistor
The circuit board designer is required to place external pull-up resistors (10 k Ω recommended) on the
SPI_DO / GPIO5 / SDA / SPI_SPD_SEL and SPI_CLK / GPIO4 / SCL lines (per SMBus 1.0
Specification and EEPROM manufacturer guidelines) to VDD33 in order to assure proper operation.
In-Circuit EEPROM Programming
The EEPROM can be programmed via automatic test equipment (ATE). Pulling nRESET low tri-states
the device’s EEPROM interface and allows an external source to program the EEPROM.
The SMSC device can be configured via its internal default configuration. Please see
"EEPROM Data Descriptor"
Table 8.1
There are three different resets that the device experiences. One is a hardware reset from the internal
power-on reset (POR) circuit, another reset is via the nRESET pin, and the third is a USB bus reset.
Internal POR Hardware Reset
All reset timing parameters are guaranteed by design.
External Hardware nRESET
A valid hardware reset is defined as assertion of nRESET for a minimum of 1 μ s after all power
supplies are within operating range. While reset is asserted, the device (and its associated external
circuitry) consumes less than 500 μ A of current.
Assertion of nRESET (external pin) causes the following:
1. All downstream ports are disabled and PRTCTL power to downstream devices is removed.
2. The PHYs are disabled and the differential pairs will be in a high-impedance state.
3. All transactions immediately terminate; no states are saved.
4. All internal registers return to the default state (in most cases, 00h).
5. The external crystal oscillator is halted.
6. The PLL is halted.
Default Configuration Option
Reset
for the internal default values that are loaded when this option is selected.
for specific details on how to enable default configuration. Please refer to
DATASHEET
51
Revision 1.0 (06-09-09)
Section 8.3.2,