FT2232HQ-REEL FTDI, FT2232HQ-REEL Datasheet
FT2232HQ-REEL
Specifications of FT2232HQ-REEL
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FT2232HQ-REEL Summary of contents
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... Mbytes/Sec CPU-style FIFO interface mode simplifies CPU interface design. MCU host bus emulation mode configuration option. Fast Opto-Isolated serial interface option. FTDI‟s royalty-free Virtual Com Port (VCP) and Direct (D2XX) drivers requirement for USB driver development in most cases. ...
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... FT2232H appear as a virtual COM port (VCP). This allows the user to communicate with the USB interface via a standard PC serial emulation port (for example TTY). Another FTDI USB driver, the D2XX driver, can also be used with application software to directly access the FT2232H through a DLL ...
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... FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC 1.2 Part Numbers Part Number FT2232HL-xxxx FT2232HQ-xxxx Note: Packaging code for xxxx is: - Reel: Taped and Reel (LQFP =1000 pcs per reel, QFN =4000 pcs per reel) -Tray: Tray packing, (LQFP =160 pcs per tray, QFN =260 pcs per tray) Please refer to section 8 for all package mechanical parameters ...
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... For a description of each function please refer to Section 4. Copyright © 2010 Future Technology Devices International Limited 120 MHz USB Protocol Engine And FIFO Control 120 MHz Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 120 MHz Baud Rate ADBUS0 Generator ADBUS1 ADBUS2 Dual Port TX ...
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... MCU Host Bus Emulation Mode Signal Timing – Read Cycle ............................................. 33 4.8 Fast Opto-Isolated Serial Interface Mode Description ...................... 35 4.8.1 Outgoing Fast Serial Data ........................................................................................... 36 4.8.2 Incoming Fast Serial Data ........................................................................................... 36 Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 5 ...
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... USB Self Powered Configuration ....................................................... 51 6.3 Oscillator Configuration .................................................................... 53 7 EEPROM Configuration ................................................................ 54 8 Package Parameters ................................................................... 55 8.1 FT2232HQ, QFN-64 Package Dimensions .......................................... 55 8.2 FT2232HL, LQFP-64 Package Dimensions ......................................... 56 8.3 Solder Reflow Profile ........................................................................ 58 9 Contact Information ................................................................... 60 Appendix A – List of Figures and Tables .................................................... 61 List of Tables ............................................................................................. 61 Appendix B – Revision History ................................................................... 63 Copyright © ...
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... ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 ACBUS0 ACBUS1 ACBUS2 ACBUS3 ACBUS4 ACBUS5 FT2232HL ACBUS6 ACBUS7 BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 BDBUS5 BDBUS6 BDBUS7 BCBUS0 BCBUS1 BCBUS2 BCBUS3 BCBUS4 BCBUS5 BCBUS6 BCBUS7 PWREN# SUSPEND# Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI# ...
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... SIWUB SIWUB SIWUB ** ** ** ** ** ** PWRSAV PWRSAV PWRSAV # # # # PWREN# PWREN# PWREN# SUSPEND SUSPEND SUSPEND # # # # Configuration memory interface Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 Fast CPU Serial Style MPSSE interface FIFO Emulation TCK/SK D0 USES TDI/DO D1 CHANNEL TDO/ TMS/CS D3 GPIOL0 D4 GPIOL1 D5 GPIOL2 D6 GPIOL3 D7 GPIOH0 ...
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... It is recommended that this supply is filtered using an LC Input filter. +3.3V Input. Integrated 1.8V voltage regulator input. Input +1.8V Output. Integrated voltage regulator output. Connect to VCORE with 3.3uF filter capacitor. 0V Analog ground. Input 0V Ground input. Input Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 Description 9 ...
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... EEPROM clock. EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to Data-Out of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the EEPROM to VCC via a 10K resistor for correct operation. Tri-State during device reset. Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 Description 10 ...
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... RXLED = Receive signaling output. Pulses low when receiving OUTPUT data (RXD) via USB. This should be connected to an LED. TXLED = Transmit signaling output. Pulses low when OUTPUT transmitting data (TXD) via USB. This should be connected to an LED. Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 11 ...
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... EEPROM must be set to make port A 245 mode. A software command (Set Bit Mode option) is then sent by the application to the FTDI driver to tell the chip to enter single channel synchronous FIFO mode. In this mode the „B‟ channel is not available as all resources have been switched onto channel A ...
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... USB on the next Bulk-IN request from the drivers regardless of the pending packet size. This can be used to optimize USB transfer speed for some applications. Tie this pin to VCCIO if not used. (Also see note section 4.12) Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 13 ...
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... The FT2232H channel A or channel B can be configured as a synchronous or asynchronous bit-bang interface. Bit-bang mode is a special FTDI FT2232H device mode that changes the 8 IO lines on either (or both) channels into an 8 bit bi-directional data bus. There are two types of bit-bang modes: synchronous and asynchronous ...
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... I/O GPIOH6 I/O GPIOH7 I/O Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 MPSSE Configuration Description Clock Signal Output. For example: JTAG – TCK, Test interface clock SPI – SK, Serial Clock Serial Data Output. For example: JTAG – TDI, Test Data Input SPI – ...
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... FT2232H Pins used as a Fast Serial Interface The FT2232H channel B can be configured for use with high-speed optical bi-directional isolated serial data transfer: Fast Serial Interface. (Not available on channel A). A proprietary FTDI protocol designed to allow galvanic isolated devices to communicate synchronously with the FT2232H using just 4 signal wires (over two dual opto-isolators), and two power lines ...
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... Copyright © 2010 Future Technology Devices International Limited Name Type I bidirectional data bus CS# INPUT Active low chip select input A0 INPUT Address bit A0 RD# INPUT Active Low FIFO Read input WR# INPUT Active Low FIFO Write input Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 Fast Serial Interface Configuration Description 17 ...
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... PC. I/O1 must be held in input mode if this option is used. Please refer to Application Note AN_108 for operation of these instructions. Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 used. 18 ...
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... FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC 4 Function Description The FT2232H USB 2.0 High Speed (480Mb/s) to UART/FIFO is one of FTDI‟s 5 the capability of being configured in a variety of industry standard serial or parallel interfaces. The FT2232H has two independent configurable interfaces. Each interface can be configured as UART, FIFO, JTAG, SPI, I2C or bit-bang mode with independent baud rate generators ...
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... VCC = +3.00V to 3.6V. The EEPROM is programmable in-circuit over USB using a utility program called MPROG available from FTDI‟s web site (www.ftdichip.com). This allows a blank part to be soldered onto the PCB and programmed as part of the manufacturing and test process. ...
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... FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC 4.3 Dual Port FT232 UART Interface Mode Description The FT2232H can be configured in similar UART modes as the FTDI FT232 devices. The following examples illustrate how to configure the FT2232H with an RS232, RS422 or RS485 interface. The FT2232 can be configured as a mixture of these interfaces ...
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... FT2232H to RS422 levels. The PWREN# signal is used to power down the level shifters such that they operate in a low quiescent current when the USB interface is in suspend mode. Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 22 ...
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... RS485 is a multi-drop network – i.e. many devices can communicate with each other over a single two wire cable connection. The RS485 cable requires to be terminated at each end of the cable. Links are Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 23 ...
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... With the FT2232H it is possible to do this entirely in hardware – simply modify the schematic so that RXD of the FT2232H is the logical OR of the level converter device receiver output with TXDEN using an HC32 or similar logic gate Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 24 ...
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... RD# setup time to CLKOUT (RD# low afterOE# low WR# setup time to CLKOUT (WR# low after TXE# low) ns Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 Description CLKOUT period CLKOUT high period CLKOUT low period CLKOUT to RXF# CLKOUT to read DATA valid OE# to read DATA valid CLKOUT to OE# RD# hold time CLKOUT TO TXE# ...
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... RD# setup time to CLKOUT (RD# low afterOE# low WR# setup time to CLKOUT (WR# low after TXE# low) ns Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 Description CLKOUT period CLKOUT high period CLKOUT low period CLKOUT to RXF# CLKOUT to read DATA valid OE# to read DATA valid CLKOUT to OE# RD# hold time CLKOUT TO TXE# ...
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... This mode does not provide a CLKOUT signal and it does not expect an OE# input signal. The following diagrams illustrate the asynchronous FIFO mode timing. Figure 4.5 FT245 asynchronous FIFO Interface READ Signal Waveforms Figure 4.6 FT245 asynchronous FIFO Interface WRITE Signal Waveforms Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 27 ...
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... TXE# inactive after WR# cycle ns DATA to WR# active setup time ns DATA hold time after WR# inactive Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 Description RD# inactive to RX# RD# to DATA RD# active pulse width RD# active after RXF# WR# active to TXE# inactive WR# active pulse width WR# active after TXE# 28 ...
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... AN_111 – “Programming Guide for High Speed FTCSPI DLL” Copyright © 2010 Future Technology Devices International Limited Maximum Units Description ns CLKOUT period ns CLKOUT high period ns CLKOUT low period 7.15 ns CLKOUT to TDI/DO delay ns TDO/DI hold time TDO/DI setup time Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 29 ...
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... Figure 4.9: Adaptive Clocking waveform. Adaptive clocking is not enabled by default. See: AN_108 Command Processor for MPSSE and MCU Host Bus Emulation Modes. Copyright © 2010 Future Technology Devices International Limited RTCK ARM CPU TDO changes on falling edge of TCK Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 30 ...
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... In Host Bus Emulation mode the clock divisor has no effect. The clock divisor is used for serial data and is a different part of the MPSSE block. In host bus emulation the 60MHz clock is always output and doesn‟t change with any commands. Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 31 ...
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... When Div the device will return 2 bytes when doing a read. When it is off the device will return 1 byte when doing a read. The clock period is 16. most devices would need the Div set on. IORDY can be held low permanently to extend all cycles. Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 32 ...
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... When Div the device will return 2 bytes when doing a read. When it is off the device will return 1 byte when doing a read. The clock period is 16. most devices would need the Div set on. IORDY can be held low permanently to extend all cycles. Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 33 ...
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... IORDY# I/O0 I/O1 Figure 4.12 MCU Host Emulation Example using a CANBus Controller Copyright © 2010 Future Technology Devices International Limited SJA1000 CANBus Tx CS# Controller ALE/AS Rx RD# WR# AD[7:0] Vcc MODE INT# Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 CANBus Transeiver CAN Bus 34 ...
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... Table 4.6 Fast Opto-Isolated Serial Interface Signal Timings Copyright © 2010 Future Technology Devices International Limited Maximu Units Description ns FSDO/FSCTS hold time ns FSDO/FSCTS setup time ns FSDI hold time ns FSDI Setup Time ns FSCLK low ns FSCLK high ns FSCLK Period Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 shown in Table 35 ...
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... The target device should ensure that CTS is high before it sends data. CTS goes low after data bit 0 (D0) and stays low until the chip can accept more data. Copyright © 2010 Future Technology Devices International Limited Data Bits - LSB first Data Bits - LSB first Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 D7 SRCE Source Bit D7 DEST Destination Bit 36 ...
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... VCC5V FT2232H FSDI 6 FSCLK 5 VCC5V 470R FSDO FSCTS 470R Figure 4.16 Fast Opto-Isolated Serial Interface Example Copyright © 2010 Future Technology Devices International Limited Cable HCPL-2430 Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 VCCE 470R DI CLK 470R VCCE 8 HCPL-2430 CTS ...
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... Copyright © 2010 Future Technology Devices International Limited RD# X Read Data Pipe Read Status Status Data available (=RXF) Space available (=TXE) Suspend Configured Valid Valid t2 t5 Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 WR# X Write Data Pipe Send Immediate Valid t6 Valid t7 38 ...
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... A0/CS Hold from WR# ns Data hold from WR# ns A0/CS Setup to RD# Data delay from RD A0/CS hold from RD Data hold time from RD# Microcontroller IO10 IO11 IO12 IO13 IO14 IO15 IO16 IO17 IO20 IO21 IO22 IO23 IO24 IO25 Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 39 ...
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... See application note AN2232-02, “Bit Mode Functions for the FT2232” for more details and examples of using the bit-bang modes. An example of the synchronous bi-bang mode timing is shown in Figure 4.19 Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 40 ...
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... Signals and data-flow are illustrated in Figure 4.20 USB Rx FIFO/ Buffer USB USB Tx FIFO/ Buffer Figure 4.20 Bit-bang Mode Dataflow Illustration Diagram. Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 WRSTB# Parallel I/O pins Parallel I/O data RDSTB# 41 ...
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... In Figure 4.22 the transmit and receive LED indicators are wire-OR‟ed together to give a single LED indicator which indicates any transmit or receive data activity. Note that the LED‟s are connected to the same supply as VCCIO. Copyright © 2010 Future Technology Devices International Limited VCCIO RX 220R VCCIO Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 42 ...
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... If remote wake-up is enabled, a peripheral is allowed to draw up to 2.5mA in suspend. If remote wake-up is disabled, the peripheral must draw no more than 500uA in suspend Pull-down is enabled, the FT2232H will not wake up from suspend. Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 43 ...
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... MPSSE used in MCU Host BUS Emulation mode. The MPSSE can be configured directly using the D2XX commands. The D2XX_Programmers_Guide is available from the FTDI website at http://www.ftdichip.com/Documents/ProgramGuides/D2XX_Programmer‟s_Guide(FT_000071).pdf The application note AN_108 – “Command Processor For MPSSE and MCU Host Bus Emulation Modes” ...
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... Parameter Storage Temperature Floor Life (Out of Bag) At Factory Ambient (30°C / 60% Relative Humidity) Ambient Operating Temperature (Power Applied) MTTF FT2232HL MTTF FT2232HQ VCORE Supply Voltage VCCIO IO Voltage DC Input Voltage – USBDP and USBDM DC Input Voltage – High Impedance Bi-directionals (powered from VCCIO) DC Input Voltage – ...
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... Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 Units Conditions V Cells are 5V V tolerant VREGIN +3.3V VCORE = +1.8V mA Normal Operation VCORE = +1.8V mA Device in reset state VCORE = +1.8V µA ...
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... Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 Units Conditions V Ioh = +/-2mA I/O Drive strength* = 4mA V I/O Drive strength* = 8mA V I/O Drive strength* = 12mA V I/O Drive strength* = 16mA V Iol = +/-2mA I/O Drive strength* = 4mA ...
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... Minimum Typical Maximum VCORE- 0.2 - 2.0 - Reference Minimum JEDEC EIA/JESD22- A114-B, Class 2 JEDEC EIA/JESD22- A115-A, Class B JESD22-C101- D, Class-III Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 Units Conditions 3.6 V 3.3V I/O High-speed operation 480 MHz 50 μA USB Suspend Units Conditions V 0.2 V 0.8 ...
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... EEDATA 2 OSCI OSCO 12MHz 13 TEST 27pF 27pF GND GND Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 +1.8V +1.8V +1.8V +3.3V +3.3V +3.3V +3.3V 100nF 100nF 100nF 100nF 100nF 100nF 100nF GND GND GND GND GND GND GND +1.8V +3.3V 16 ADBUS0 17 ADBUS1 ...
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... EEDATA 2 OSCI OSCO 2.2K 12MHz 13 TEST 27pF 27pF GND GND Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 +1.8V +1.8V +1.8V +3.3V +3.3V +3.3V +3.3V 100nF 100nF 100nF 100nF 100nF 100nF 100nF GND GND GND GND GND GND GND +1.8V +3.3V 16 ADBUS0 17 ...
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... EEDATA EEDATA 2 OSCI OSCO 12MHz 13 TEST 27pF 27pF GND GND Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 +1.8V +1.8V +1.8V +3.3V +3.3V +3.3V +3.3V 100nF 100nF 100nF 100nF 100nF 100nF 100nF GND GND GND GND GND GND GND +1.8V +3.3V 16 ADBUS0 17 ...
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... EEDATA 2 OSCI OSCO 2.2K 12MHz 13 TEST 27pF 27pF GND GND Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 +1.8V +1.8V +1.8V +3.3V +3.3V +3.3V +3.3V 100nF 100nF 100nF 100nF 100nF 100nF 100nF GND GND GND GND GND GND +1.8V +3.3V 16 ADBUS0 17 ADBUS1 ...
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... Input Voltage FIn Input Frequency Ji Cycle to cycle jitter Table 6.1 OSCI Input characteristics Copyright © 2010 Future Technology Devices International Limited Minimum Typical Maximum 2.97 3.30 3.63 12 < 150 Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 Units Conditions V +/- 30ppm MHz pS 53 ...
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... If an external EEPROM is fitted (93LC46/56/66) it can be programmed over USB using MPROG V3.4a or later. The EEPROM must be 16 bits wide and capable or working at a VCC supply of +3.0 to +3.6 volts. Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 54 ...
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... FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC 8 Package Parameters The FT2232H is available in two different packages. The FT2232HL is the LQFP-64 option and the FT2232HQ is the QFN-64 package option. The solder reflow profile for both packages is described in Section 8.3 8.1 FT2232HQ, QFN-64 Package Dimensions Top View ...
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... Copyright © 2010 Future Technology Devices International Limited Top View 49 48 FTDI YYWW - 10.000+/- 0.1 Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 Line 1 – FTDI Logo Line 2 – Date Code and Revision Line 3 – Wafer Lot Number Line 4 – FTDI Part Number Dimensions are body dimensions (mm) 56 ...
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... BSC Table 8.1 64 pin LQFP Package Details – dimensions (in mm) Copyright © 2010 Future Technology Devices International Limited MAX 12.2 10.1 12.2 10.1 0.27 0.2 0.23 0.16 Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 57 ...
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... FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC 8.3 Solder Reflow Profile Figure 8.3 64 pin LQFP and QFN Reflow Solder Profile Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 58 ...
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... Max. 8 minutes Max. p Volume mm3 < 350 235 +5/-0 deg C 220 +5/-0 deg C Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 SnPb Eutectic and Pb free (non green material) Solder Process 3°C / Second Max. 100°C 150° 120 seconds 183° 150 seconds see Table 8 ...
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... E-Mail (General Enquiries): cn.admin1@ftdichip.com Web Site URL: http://www.ftdichip.com Distributor and Sales Representatives Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country. Copyright © 2010 Future Technology Devices International Limited Document No ...
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... Table 8.3 Package Reflow Peak Temperature .................................................................................. 59 List of Figures Figure 2.1 FT2232H Block Diagram ................................................................................................. 4 Figure 3.1 FT2232H Schematic Symbol ...................................................................................... 7 Figure 4.1 RS232 Configuration .................................................................................................... 21 Figure 4.2 Dual RS422 Configuration ............................................................................................. 22 Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 61 ...
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... Figure 6.5 Recommended FT2232H Crystal Oscillator Configuration. ................................................. 53 Figure 8.1 64 pin QFN Package Details .......................................................................................... 55 Figure 8.2 64 pin LQFP Package Details ......................................................................................... 57 Figure 8.3 64 pin LQFP and QFN Reflow Solder Profile ..................................................................... 58 Copyright © 2010 Future Technology Devices International Limited Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 62 ...
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... Interface timing diagram. Edited section 4.3.2, 4.3.3, figure 4.2 and 4.3. Copyright © 2010 Future Technology Devices International Limited ( Section 1.3) „WR‟ to „WR#‟ throughtout the datasheet Document No.: FT_000061 Datasheet Version 2.10 Clearance No.: FTDI#77 October 2008 rd 23 October 2008 th 4 November 2008 ...