ADXL210AQC-1 Analog Devices Inc, ADXL210AQC-1 Datasheet - Page 8

• Manufacturer Part Number: ADXL210AQC-1
• Description: IC ACCELEROMETER DUAL 14CERPAK
• Manufacturer: Analog Devices Inc

Specifications of ADXL210AQC-1

• Rohs Status: RoHS non-compliant
• Axis: X, Y
• Acceleration Range: ±10g
• Sensitivity: 100mV/g
• Voltage - Supply: 3 V ~ 5.25 V
• Output Type: Analog
• Bandwidth: 6kHz
• Mounting Type: Surface Mount
• Package / Case: 14-CerPak
• Interface: -

initial offset. The easiest way to null this offset is with a calibra-
tion factor saved on the microcontroller or by a user calibration
for zero g. In the case where the offset is calibrated during manu-
facture, there are several options, including external EEPROM
and microcontrollers with “one-time programmable” features.
DESIGN TRADE-OFFS FOR SELECTING FILTER
CHARACTERISTICS: THE NOISE/BW TRADE-OFF
The accelerometer bandwidth selected will determine the mea-
surement resolution (smallest detectable acceleration). Filtering
can be used to lower the noise floor and improve the resolution
of the accelerometer. Resolution is dependent on both the ana-
log filter bandwidth at X
microcontroller counter.
The analog output of the ADXL202/ADXL210 has a typical
bandwidth of 5 kHz, much higher than the duty cycle stage is
capable of converting. The user must filter the signal at this
point to limit aliasing errors. To minimize DCM errors the
analog bandwidth should be less than 1/10 the DCM frequency.
Analog bandwidth may be increased to up to 1/2 the DCM
frequency in many applications. This will result in greater dy-
namic error generated at the DCM.
The analog bandwidth may be further decreased to reduce noise
and improve resolution. The ADXL202/ADXL210 noise has
the characteristics of white Gaussian noise that contributes
equally at all frequencies and is described in terms of g per root
Hz; i.e., the noise is proportional to the square root of the band-
width of the accelerometer. It is recommended that the user limit
bandwidth to the lowest frequency needed by the application, to
maximize the resolution and dynamic range of the accelerometer.
With the single pole roll-off characteristic, the typical noise of
the ADXL202/ADXL210 is determined by the following equation:
At 100 Hz the noise will be:
Often the peak value of the noise is desired. Peak-to-peak noise
can only be estimated by statistical methods. Table III is useful
for estimating the probabilities of exceeding various peak values,
given the rms value.
The peak-to-peak noise value will give the best estimate of the
uncertainty in a single measurement.
ADXL202/ADXL210
Noise rms
Nominal Peak-to-Peak
Value
2.0
4.0
6.0
8.0
Table III. Estimation of Peak-to-Peak Noise
Noise rms
rms
rms
rms
rms
500 g / Hz
FILT
500 g / Hz
and Y
% of Time that Noise
Will Exceed Nominal
Peak-to-Peak Value
32%
4.6%
0.27%
0.006%
FILT
100
and on the speed of the
BW 1.5
(1.5)
6.12 mg
–8–
Table IV gives typical noise output of the ADXL202/ADXL210
for various C
Bandwidth
10 Hz
50 Hz
100 Hz
200 Hz
500 Hz
CHOOSING T2 AND COUNTER FREQUENCY: DESIGN
TRADE-OFFS
The noise level is one determinant of accelerometer resolution.
The second relates to the measurement resolution of the
counter when decoding the duty cycle output.
The ADXL202/ADXL210’s duty cycle converter has a resolu-
tion of approximately 14 bits; better resolution than the acceler-
ometer itself. The actual resolution of the acceleration signal is,
however, limited by the time resolution of the counting devices
used to decode the duty cycle. The faster the counter clock, the
higher the resolution of the duty cycle and the shorter the T2
period can be for a given resolution. The following table shows
some of the trade-offs. It is important to note that this is the
resolution due to the microprocessors’s counter. It is probable
that the accelerometer’s noise floor may set the lower limit on
the resolution, as discussed in the previous section.
Table V. Trade-Offs Between Microcontroller Counter Rate,
T2 Period and Resolution of Duty Cycle Modulator
T2 (ms) (k ) Rate
1.0
1.0
1.0
5.0
5.0
5.0
10.0
10.0
10.0
Table IV. Filter Capacitor Selection, C
R
124
124
124
625
625
625
1250 100
1250 100
1250 100
SET
X
and C
C
0.47 F
0.10 F
0.05 F
0.027 F 8.7 mg
0.01 F
ADXL202/ Counter-
ADXL210 Clock
Sample
1000
1000
1000
200
200
200
X
, C
Y
Y
values.
Rate
(MHz)
2.0
1.0
0.5
2.0
1.0
0.5
2.0
1.0
0.5
rms Noise
1.9 mg
4.3 mg
6.1 mg
13.7 mg
Counts
per T2
Cycle
2000
1000
500
10000
5000
2500
20000
10000
5000
Peak-to-Peak Noise
Estimate 95%
Probability (rms
7.6 mg
17.2 mg
24.4 mg
35.8 mg
54.8 mg
Counts Resolution
per g
250
125
62.5
1250
625
312.5
2500
1250
625
X
and C
(mg)
4.0
8.0
16.0
0.8
1.6
3.2
0.4
0.8
1.6
Y
REV. B
4)