CS5330A-KSZ Cirrus Logic Inc, CS5330A-KSZ Datasheet
CS5330A-KSZ
Specifications of CS5330A-KSZ
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CS5330A-KSZ Summary of contents
Page 1
... The output sample rate can be infinitely adjusted between 2 kHz and 50 kHz. The CS5330A/31A operates from a single +5 V supply and requires only 150 mW for normal operation, making it ideal for battery-powered applications. The ADC uses delta-sigma modulation with 128X over- sampling, followed by digital filtering and decimation, which removes the need for an external anti-alias filter ...
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... Data Output Timing - CS5331A (I²S Compatible) ....................................................... 10 Figure 4. CS5330A/31A Initialization and Power-Down Sequence............................................ 12 Figure 5. CS5330A/31A Digital Filter Stopband Rejection......................................................... 13 Figure 6. CS5330A/31A Digital Filter Transition Band ............................................................... 13 Figure 7. CS5330A/31A Digital Filter Passband Ripple ............................................................. 13 Figure 8. CS5330A/31A Digital Filter Transition Band ............................................................... 13 LIST OF TABLES Table 1. Common Clock Frequencies......................................................................................... 9 2 CS5330A/31A ...
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... Audio Serial Data Output (Output) - Two’s complement MSB-first serial data is output on this SDATA 1 pin kΩ resistor on this pin will place the CS5330A/31A into Master Mode. Serial Data Clock (Input/Output) - SCLK is an input clock at any frequency from 32x to 64x the SCLK output word rate ...
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... The maximum over/under voltage is limited by the input current. 4 Symbol Min VA+ 4.75 -10 KS, KSZ T A -40 BS, DS (Note 1) Symbol Min VA+ -0.3 lin - (Note 2) V -0.7 (Note 3) INA V -0.7 (Note 3) IND T - -65 stg CS5330A/31A Typ Max Unit 5.0 5. +70 °C - +85 °C Typ Max Unit - +6 ± VA+0 VA+0 +125 °C - +150 °C ...
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... Referenced to typical full-scale input voltage. 5. Internal highpass filter removes offset. DS138F5 5330A/31A-KS/KSZ Symbol Min Typ -84 THD+N - -72 - -32 THD - 0.003 - 0 150 - - VIN 3.6 4.0 ZIN - 100 2.2 2.4 VA+ IA 100 - 150 - 0.5 PSRR - 50 CS5330A/31A 5331A-DSZ Max Min Typ Max - - - -32 26 0.02 - 0.003 0 0.1 - ± ± 150 - ...
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... The analog modulator samples the input at 6.144 MHz for an output sample rate of 48 kHz. There is no rejection of input signals which are multiples of the sampling frequency (n x 6.144 MHz ±21.7 kHz where n = 0,1,2,3…). 8. Group delay for kHz Symbol (0.05) (Note 6) (Note 6) (Note 7) (Note 8) (Note 6) (Note 6) = 15/48 kHz = 312µs. gd CS5330A/31A Min Typ Max VA-1 ...
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... MCLK/LRCK = 256 t clkw MCLK/LRCK = 384 t clkl MCLK/LRCK = 384 t clkh MCLK/LRCK = 384 t clkw MCLK/LRCK = 512 t clkl MCLK/LRCK = 512 t clkh MCLK/LRCK = 512 t mslr t sdo t clkw t clkl t clkh t dss t lrdss t slr1 t slr2 CS5330A/31A Min Typ Max 1000 31 - 1000 31 - 1000 52 - 1000 20 - 1000 20 - 1000 39 - 1000 13 - 1000 13 - 1000 - ...
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... SDATA SCLK to SDATA LRCK - MASTER mode (CS5330A slr1 slr2 SCLK input (SLAVE mode) LRCK input (SLAVE mode) t lrdss MSB SDATA SCLK to LRCK & SDATA - SLAVE mode (CS5330A) +5V Analog 10 µ F .47 µ F 150 Ω ** .01 µ F Analog Input Circuits .47 µ F 150 Ω ** .01 µ F ...
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... In Master mode, SCLK and LRCK are outputs which are internally derived from MCLK. The CS5330A/31A will divide MCLK generate a SCLK which is 64× Fs and by 256 to generate LRCK. The CS5330A and CS5331A can be placed in the Master mode with a 47 kohm pull-down resistor on the SDATA pin as shown in Figure 1 ...
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... LRCK transitions and the MSB of the data. The falling edges of SCLK cause the ADC to output the eigh- teen data bits. The data bits are valid during the rising edge of SCLK. LRCK is also inverted compared to the CS5330A interface. The CS5331A interface is compatible with I LRCK ...
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... AINR and AINL pins. Each analog input will accept a maximum of 4 Vpp centered at +2.4 V. The CS5330A/31A samples the analog inputs at 128 × Fs, 6.144 MHz for a 48 kHz sample-rate. The dig- ital filter rejects all noise above 29 kHz except for frequencies right around 6.144 MHz ±21.7 kHz (and multiples of 6.144 MHz). Most audio signals do not have significant energy at 6.144 MHz. Nevertheless, a 150 Ω ...
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... Figure 4. CS5330A/31A Initialization and Power-Down Sequence The CS5330A and CS5331A have a Power-Down mode wherein typical consumption drops to 0.5 mW. This is initiated when a loss of clock is detected on either the LRCK or MCLK pins in Slave Mode, or the MCLK pin in Master Mode. The initialization sequence will begin when MCLK, and LRCK for slave mode, are restored ...
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... Figure 6. CS5330A/31A Digital Filter Transition Band 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 0.40 0.4 0.5 Figure 8. CS5330A/31A Digital Filter Transition Band CS5330A/31A .47 .48 .49 .50 .51 .52 .53 Normalized Input Frequency 0.45 0.50 0.60 0.65 Normalized Input Frequency .54 ...
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... The deviation of the measured full-scale amplitude from the ideal full-scale amplitude value. Gain Drift The change in gain value with temperature. Units in ppm/°C. Bipolar Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in LSBs. 14 CS5330A/31A DS138F5 ...
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... TYP 0 0.25 0 1.77 1.88 0.070 0.33 0.51 0.013 .15 0.25 0.006 0° 8° 0° 5.18 5.4 0.204 0.48 0.76 0.019 7.67 8.1 0.302 CS5330A/31A G I Inches MAX 0.210 0.050 TYP 0.010 0.074 0.020 0.010 8° 0.213 0.030 0.319 15 ...
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... CS5330A/31A Container Order # Bulk CS5330A-KS Tape & Reel CS5330A-KSR Bulk CS5331A-KS Tape & Reel CS5331A-KSR Bulk CS5330A-KSZ Tape & Reel CS5330A-KSZR Bulk CS5331A-KSZ Tape & Reel CS5331A-KSZR Bulk CS5330A-BS Tape & Reel CS5330A-BSR Bulk CS5331A-DSZ Tape & Reel CS5331A-DSZR DS138F5 ...