CS5330A-KSZ Cirrus Logic Inc, CS5330A-KSZ Datasheet - Page 12

• Manufacturer Part Number: CS5330A-KSZ
• Description: IC, ADC, 18BIT, 50KSPS, SOIC-8
• Manufacturer: Cirrus Logic Inc

Specifications of CS5330A-KSZ

• Resolution (bits): 18bit
• Sampling Rate: 50kSPS
• Input Channel Type: Single Ended
• Data Interface: Serial
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Supply Current: 30mA
• Digital Ic Case Style: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3.1.10 Grounding and Power Supply Decoupling
USER: Re move
MCLK
The CS5330A and CS5331A have a Power-Down mode wherein typical consumption drops to 0.5 mW.
This is initiated when a loss of clock is detected on either the LRCK or MCLK pins in Slave Mode, or the
MCLK pin in Master Mode. The initialization sequence will begin when MCLK, and LRCK for slave mode,
are restored. In slave mode power-down, the CS5330A and CS5331A will adapt to changes in
MCLK/LRCK frequency ratio during the initialization sequence. It is recommended that clocks not be ap-
plied to the device prior to power supply settling. A reset circuit may be implemented by gating the MCLK
signal.
As with any high resolution converter, the ADC requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 1 shows the recommended power ar-
rangements with VA+ connected to a clean +5V supply. Decoupling capacitors should be as near to the
ADC as possible, with the low value ceramic capacitor being the nearest. To minimize digital noise, con-
nect the ADC digital outputs only to CMOS inputs. The printed circuit board layout should have separate
analog and digital regions and ground planes. An evaluation board, CDB5330A or CDB5331A, is avail-
able which demonstrates the optimum layout and power supply arrangements, as well as allowing fast
evaluation of the CS5330A and CS5331A.
Initia
- Hi gh p a ss f i l t er settin
- S DATA mut e rele
MCLK/ LRCK R ati o
l i zati on
Mast er Mode
Figure 4. CS5330A/31A Initialization and Power-Down Sequence
Power Down
Di gita l Out put
i s gener at e d
i s 256x o n ly
Mast er Mode
ased
gs
USER: Apply Power
Initia
USER: Apply
Mast er / Sl ave
l Power
Deci si on
-D own
MCLK
Sl ave Mode
Initia
- Hi gh p a ss f i l t er settin
- S DATA mut e rele
MCLK/ LRCK R ati o
l i zati on
Di gita l Out put
i s Gener at e d
Det er minati
Power Down
256 / 384 / 512
Sl ave Mode
on
USER: Apply
an d LRCK
ased
g
MCLK
MCLK, LRCK or Bot h
CS5330A/31A
USER: Re move
DS138F5