CS4341-KS Cirrus Logic Inc, CS4341-KS Datasheet
CS4341-KS
Specifications of CS4341-KS
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CS4341-KS Summary of contents
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... The CS4341 accepts data at audio sample rates from 2 kHz to 100 kHz, consumes very little power and oper- ates over a wide power supply range. These features are ideal for DVD, A/V receiver and set-top box systems. ORDERING INFORMATION CS4341-KS CDB4341 AD0/CS MUTEC External ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS4341 DS298PP2 ...
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... C Mode Control Port Formating ................................................................................ 27 Figure 9. Base-Rate Stopband Rejection .................................................................................... 28 Figure 10. Base-Rate Transition Band .......................................................................................... 28 Figure 11. Base-Rate Transition Band (Detail) ............................................................................. 28 Figure 12. Base-Rate Passband Ripple ........................................................................................ 28 Figure 13. High-Rate Stopband Rejection .................................................................................... 28 Figure 14. High-Rate Transition Band ........................................................................................... 28 Figure 15. High-Rate Transition Band (Detail) .............................................................................. 29 Figure 16. High-Rate Passband Ripple ......................................................................................... 29 Figure 17. Output Test Load ......................................................................................................... 29 DS298PP2 CS4341 3 ...
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... Figure 20. CS4341 Format 0 (I Figure 21. CS4341 Format 1 (I Figure 22. CS4341 Format 2 ......................................................................................................... 30 Figure 23. CS4341 Format 3 ......................................................................................................... 31 Figure 24. CS4341 Format 4 ......................................................................................................... 31 Figure 25. CS4341 Format 5 ......................................................................................................... 31 Figure 26. CS4341 Format 6 ......................................................................................................... 32 Figure 27. De-Emphasis Curve ..................................................................................................... 32 Figure 28. ATAPI Block Diagram .................................................................................................. 32 LIST OF TABLES Table 1. Master Clock Divide Enable ............................................................................................... 15 Table 2 ...
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... Logic "1" Logic "0" = AGND; A Base-rate Mode Symbol Min T -10 A (Note 1) unweighted 92 A-Weighted 96 - A-Weighted - (Note 1) THD - - - - kHz -10 A (Note 1) unweighted 99 A-Weighted 102 - A-Weighted - (Note 1) THD - - - - kHz) - CS4341 High-Rate Mode Typ Max Min Typ - 70 - 101 - 95 100 -89 -84 - -89 -77 -72 - -74 -37 -32 - -36 - -89 - -73 - -34 100 - - 100 - 70 - ...
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... Min Typ Max 0.63•VA 0.7•VA 0.77•VA - 0.5• 0 100 - 100 L High-Rate Mode Typ Max Min Typ - .4535 - - - - .4998 +.08 -0. .577 - - - ±1.39/ ±0.23/Fs - +.2/-.1 - +.05/-.14 (Note 6) - +0/-.22 CS4341 Units Vpp VDC dB ppm/° Max Unit - Fs .4621 Fs .4982 DS298PP2 ...
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... I A power-down state I A (Note 7) normal operation power-down JA (Note 8) PSRR (60 Hz) as shown in Figure 25° 2.7V - 5.5V) A Symbol (AGND = 0V; all voltages with respect to ground.) Symbol IND stg (AGND = 0V; all voltages with respect to ground.) Symbol VA CS4341 Typ Max Units - 0 0. 110 - °C/Watt - 60 - ...
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... Figures 20-26 -10 to 70° 2.7V - 5.5V; Inputs: Logic 0 = 0V, A Symbol Fs MCLK/LRCK = 512 MCLK/LRCK = 512 t sclkl t sclkh t sclkw t sclkw t slrd t slrs t sdlrs t sdh (Note 9) (Note 10) t sclkw t sclkr t sdlrs t sdh t sdh CS4341 Min Typ Max 2 - 100 10 - 1000 10 - 1000 21 - 1000 21 - 1000 31 - 1000 31 - 1000 ...
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... LRCK SCLK SDATA LRCK SDATA *INTERNAL SCLK *The SCLK pulses shown are internal to the CS4341. LRCK MCLK *INTERNAL SCLK SDATA * The SCLK pulses shown are internal to the CS4341. DS298PP2 t slrs t slrd t t sdlrs Figure 1. External Serial Mode Input Timing t sclkr t t sdlrs sdh Figure 2 ...
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... Repeated t high t hdst sud low hdd 2 Figure Control Port Timing = 30 pF) L Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 300 f 4.7 - Stop Start susp hdst t sust t r CS4341 Unit kHz ns µs µs µs µs µs µs ns µs ns µs DS298PP2 ...
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... Figure 5. SPI Control Port Timing CS4341 = 30 pF) L Min Max - 6 500 - 500 - 1 100 - 100 = 0 at all other times. spi t csh Unit MHz ns ns µ ...
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... RST 0.1 µF 1 µ 3.3 µF 560 15 AOUTA + 10 k CS4341 MUTEC 16 9 FILT 0.1 µF .1 µF 1 µ REF_GND 3.3 µF 560 12 AOUTB + 10 k AGND 13 Figure 6. Typical Connection Diagram CS4341 Audio Output OPTIONAL MUTE CIRCUIT + 1 µF Audio Output 560 Fs(R 560) L DS298PP2 ...
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... De-Emphasis POR (Power on/off Quiescent Voltage ramp) Default = ‘1’ Disabled 1 - Enabled PDN (Power-Down) Default =’1’ Disabled 1 - Enabled DS298PP2 Reserved Reserved DIF1 DIF0 DEM1 24-bit data Internal SCLK 24-bit data Internal SCLK CS4341 Reserved MCLKDIV Reserved DEM0 POR PDN ...
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... Default = ‘0’ (Refer to Table 11 ATAPI4 ATAPI3 Mode Changes take effect immediately Changes take effect on zero crossings Changes take effect with a soft ramp (default) Changes take effect in 1/8 dB steps on each zero crossing VOL5 VOL4 VOL3 CS4341 ATAPI2 ATAPI1 ATAPI0 VOL2 VOL1 VOL0 DS298PP2 ...
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... Mute Control pin will go active during the mute period. The muting function is effected, similiar to volume control changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register. AMUTE 0 Disabled 1 Enabled Table 2. Auto-Mute Enable DS298PP2 Reserved Reserved MODE DIF1 DIF0 DEM1 MODE CS4341 Reserved MCLKDIV Reserved DEM0 POR PDN 15 ...
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... 24-bit data Internal SCLK 24-bit data Internal SCLK Left Justified 24-bit data Right Justified, 24-bit Data Right Justified, 20-bit Data Right Justified, 16-bit Data Right Justified, 18-bit Data Identical to Format 1 Table 3. Digital Interface Formats DIF1 DIF0 DEM1 DESCRIPTION CS4341 DEM0 POR PDN FORMAT FIGURE ...
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... The contents of the control registers are retained in this mode. PDN 0 Disabled 1 Enabled Table 6. Power Down Enable DS298PP2 DIF1 DIF0 DEM1 MODE DIF1 DIF0 DEM1 MODE CS4341 DEM0 POR PDN DEM0 POR PDN 17 ...
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... The zero cross function is indepently monitored and implemented for each channel ATAPI4 ATAPI3 MODE ATAPI4 ATAPI3 CS4341 ATAPI2 ATAPI1 ATAPI0 ATAPI2 ATAPI1 ATAPI0 DS298PP2 ...
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... Volume and Mixing Control Register (address 02h Soft Zero Cross Access and write only in SPI. Default: 01001 - AOUTA=aL, AOUTB=bR (Stereo) Function: The CS4341 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 9 and Figure 28 for additional information. ATAPI4 ATAPI3 ATAPI2 ATAPI1 ...
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... Mute function is enabled for both channels. MUTE 0 Disabled 1 Enabled Table 10. Mute Enable 20 ATAPI0 AOUTA 1 0 MUTE 1 1 MUTE [(aL+bR)/ [(aL+bR)/ [(bL+aR)/ [(aL+bR)/ VOL5 VOL4 VOL3 MODE CS4341 AOUTB bL [(aL+bR)/2] MUTE bR bL [(bL+aR)/2] MUTE bR bL [(aL+bR)/2] MUTE bR bL [(aL+bR)/ VOL2 VOL1 VOL0 DS298PP2 ...
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... Soft and Zero Cross bits in the Volume and Mixing Control register. All volume settings less than - 94 dB are equivalent to enabling the Mute bit. Binary Code Decimal Value 0000000 0010100 0101000 0111100 1011010 Table 11. Digital Volume Settings DS298PP2 VOL5 VOL4 VOL3 Volume Setting - - - -90 dB CS4341 VOL2 VOL1 VOL0 21 ...
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... MUTEC Mute Control AOUTA Analog Output A VA Analog Power AGND Analog Ground AOUTB Analog Output B REF_GND Reference Ground VQ Quiescent Voltage FILT+ Positive Voltage Reference is not intended to supply external current CS4341 Q DS298PP2 ...
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... HRM 256x* 384x* 256x 8.1920 12.2880 8.1920 11.2896 16.9344 11.2896 12.2880 18.4320 12.2880 16.3840 24.5760 - 22.5792 33.8688 - 24.5760 36.8640 - Table 12. Common Clock Frequencies CS4341 BRM 384x 512x 768x* 12.2880 16.3840 24.5760 16.9344 22.5792 32.7680 18.4320 24.5760 36.8640 - - - - - - - - - 1024x* 32 ...
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... LRCK. External Serial Clock Mode The CS4341 will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK. ...
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... DS298PP2 6.4 Use of the Power ON/OFF Quiescent Voltage Ramp The CS4341 uses a novel technique to minimize the effects of output transients during power-up and power-down. This technique, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients com- monly produced by single-ended single-supply converters ...
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... The control port has 2 modes: SPI and I ible, with the CS4341 operating as a slave device in 2 both modes operation is desired, AD0/CS should be tied AGND. If the CS4341 ever detects a high to low transition on AD0/CS after power-up, SPI mode will be selected. The control port registers are write-only in SPI mode. 7.1 ...
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... MSB R/W byte 1 MAP = Memory Address Pointer Figure 7. SPI Mode Control Port Formating Note 1 ADDR DATA R/W ACK ACK AD0 1-8 2 Figure Mode Control Port Formating CS4341 2 1 MAP2 MAP1 0 0 DATA LSB byte n DATA ACK 1-8 Stop 0 MAP0 0 27 ...
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... Figure 9. Base-Rate Stopband Rejection Figure 11. Base-Rate Transition Band (Detail) Figure 13. High-Rate Stopband Rejection 28 Figure 10. Base-Rate Transition Band Figure 12. Base-Rate Passband Ripple Figure 14. High-Rate Transition Band CS4341 DS298PP2 ...
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... Figure 15. High-Rate Transition Band (Detail) AGND 125 100 75 Safe Operating 50 Region 25 2 Resistive Load -- R Figure 18. Maximum Loading DS298PP2 Figure 16. High-Rate Passband Ripple 3.3 µF + AOUTx R L Figure 17. Output Test Load Figure 19. Power vs. Sample Rate (VA = 5V) CS4341 V out Sample Rate (kHz) 100 29 ...
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... Left Justified 24-Bit DataINT SCLK = MCLK/LRCK = 512, 256 or 128INT SCLK = MCLK/LRCK = 384 or 192 LSB MSB - 24-Bit DataData Valid on Rising Edge 24-Bit data SCLK Figure 20. CS4341 Format LSB MSB - 24-Bit DataData Valid on Rising Edge 24-Bit data SCLK Figure 21. CS4341 Format LSB MSB - ...
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... Right Justified, 20-Bit DataData Valid on Rising Edge of SCLKSCLK Must Have at Least 40 Cycles per LRCK Period Figure 24. CS4341 Format Right Justified, 16-Bit DataData Valid on Rising Edge of SCLKSCLK Must Have at Least 32 Cycles per LRCK Period Figure 25. CS4341 Format 5 CS4341 Right Channel External SCLK Mode Right Channel ...
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... MCLK/LRCK = 384 or 192 Left Channel Audio Data Right Channel Audio Data Right Justified, 18-Bit DataData Valid on Rising Edge of SCLKSCLK Must Have at Least 36 Cycles per LRCK Period Figure 26. CS4341 Format 6 Gain dB T1=50 µs 0dB -10dB F1 F2 3.183 kHz 10.61 kHz Figure 27. De-Emphasis Curve ...
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... Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters” by Steven Harris. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 2) CDB4341 Evaluation Board Datasheet 2 3) “The I C Bus Specification: Version 2.0” Philips Semiconductors, December 1998. http://www.semiconductors.philips.com DS298PP2 CS4341 33 ...
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... JEDEC # : MS-012 CS4341 c L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.02 1.52 5.80 6 ...
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Notes • ...
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