CAT9555WI-T1 CATALYST SEMICONDUCTOR, CAT9555WI-T1 Datasheet - Page 10

• Manufacturer Part Number: CAT9555WI-T1
• Description: IC, I/O EXPANDER, 16BIT, 400KHZ, SOIC-24
• Manufacturer: CATALYST SEMICONDUCTOR

Specifications of CAT9555WI-T1

• Chip Configuration: 16 Bit
• Bus Frequency: 400kHz
• Ic Interface Type: I2C, SMBus
• No. Of I/o's: 16
• Supply Voltage Range: 2.3V To 5.5V
• Digital Ic Case Style: SOIC
• No. Of Pins: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CAT9555
ACKNOWLEDGE
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data. The SDA line remains stable LOW during
the HIGH period of the acknowledge related clock
pulse (Figure 7).
The CAT9555 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each data byte.
When the CAT9555 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT9555 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition. The master must then issue a stop
condition to return the CAT9555 to the standby power
mode and place the device in a known state.
REGISTERS AND BUS TRANSACTIONS
The CAT9555 internal registers and their address and
function are shown in Table 1.
Table 1. Register Command Byte
Doc. No. MD-9003 Rev. J
Command (hex)
FROM TRANSMITTER
FROM RECEIVER
0h
1h
2h
3h
4h
5h
6h
7h
DATA OUTPUT
DATA OUTPUT
SCL FROM
MASTER
Register
Input Port 0
Input Port 1
Output Port 0
Output Port 1
Polarity Inversion Port 0
Polarity Inversion Port 1
Configuration Port 0
Configuration Port 1
START
BUS RELEASE DELAY (TRANSMITTER)
1
Figure 7. Acknowledge Timing
ACK DELAY (≤ t
10
AA
The command byte is the first byte to follow the device
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine
which register will be written or read.
The input port register is a read only port. It reflects
the incoming logic levels of the I/O pins, regardless of
whether the pin is defined as an input or an output by
the configuration register. Writes to the input port
register are ignored.
Table 2. Registers 0 and 1 – Input Port Registers
Table 3. Registers 2 and 3 – Output Port Registers
Table 4. Registers 4 and 5 – Polarity Inversion
Registers
Table 5. Registers 6 and 7 – Configuration
Registers
)
8
default
default
default
default
default
default
default
default
bit
bit
bit
bit
bit
bit
bit
bit
N
N
O
O
I
I
C
C
0.7
X
1.7
X
0
0
1
1
1
1
0.7
1.7
0.7
1.7
0.7
1.7
9
ACK SETUP (≥ t
N
N
I
I
O
O
X
X
0.6
1.6
0
0
C
C
1
1
0.6
1.6
0.6
1.6
1
1
0.6
1.6
I
I
N
N
0.5
X
1.5
X
BUS RELEASE DELAY (RECEIVER
O
O
0
0
0.5
1.5
C
C
1
1
0.5
1.5
1
1
0.5
1.5
Characteristics subject to change without notice
I
I
SU:DAT
X
X
0.4
1.4
N
N
O
O
0
0
0.4
1.4
1
1
C
C
0.4
1.4
1
1
0.4
1.4
I
I
)
0.3
X
1.3
X
N
N
© 2010 SCILLC. All rights reserved
0
0
O
O
0.3
1.3
1
1
0.3
1.3
C
C
1
1
0.3
1.3
I
I
0.2
X
1.2
X
N
N
0
0
0.2
1.2
O
O
1
1
0.2
1.2
C
C
I
I
1
1
X
X
0.1
1.1
0.2
1.2
N
N
0
0
0.1
1.1
O
O
1
1
0.1
1.1
I
I
C
C
X
X
0.0
1.0
1
1
N
N
0.1
1.1
)
0
0
0.0
1.0
O
O
1
1
0.0
1.0
C
C
1
1
0.0
1.0