M4A5-192/96-10VNC LATTICE SEMICONDUCTOR, M4A5-192/96-10VNC Datasheet - Page 5

• Manufacturer Part Number: M4A5-192/96-10VNC
• Description: MACH4 ISP EEPLD, SMD, TQFP144, 5V
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: IspMACH 4Ar

Specifications of M4A5-192/96-10VNC

• No. Of Macrocells: 192
• No. Of I/o's: 96
• Propagation Delay: 10ns
• Frequency: 100MHz
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: 0°C To +70°C
• Logic Case: RoHS Compliant

FUNCTIONAL DESCRIPTION
The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized
PAL
communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL
blocks and central switch matrix allow the logic designer to create large designs in a single
device instead of having to use multiple devices.
The key to being able to make effective use of these devices lies in the interconnect schemes.
In the ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms
through the logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the
output switch matrix. In addition, more input routing options are provided by the input switch
matrix. These resources provide the flexibility needed to fit designs efficiently.
Notes:
1. 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page).
2. Block clocks do not go to I/O cells in M4A(3,5)-32/32.
3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do
not connect to the central switch matrix.
®
blocks interconnected by a central switch matrix. The central switch matrix allows
Clock/Input
Dedicated
Note 3
Input Pins
Pins
Figure 1. ispMACH 4A Block Diagram and PAL Block Structure
33/
34/
36
Generator
Switch
Matrix
Clock
Logic
Array
Input
with XOR
ispMACH 4A Family
Allocator
Logic
16
4
16
PAL Block
PAL Block
Macrocells
Output/
Buried
16
Note 2
Note 1
16
8
PAL Block
17466G-001
Pins
Pins
Pins
I/O
I/O
I/O
5