IS43DR16160A-37CBL INTEGRATED SILICON SOLUTION (ISSI), IS43DR16160A-37CBL Datasheet - Page 31

no-image

IS43DR16160A-37CBL

Manufacturer Part Number
IS43DR16160A-37CBL
Description
SDRAM, DDR2, 16M X 16, 1.8V, 84BGA
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet

Specifications of IS43DR16160A-37CBL

Access Time
450ps
Page Size
256Mbit
Memory Case Style
BGA
No. Of Pins
84
Memory Type
SDRAM
Memory Configuration
4 BLK (4M X 16)
Operating Temperature Range
0°C To +70°C
Frequency
266MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IS43DR16160A-37CBL
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS43DR16160A-37CBL
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS43DR16160A-37CBL-TR
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS43DR16160A-37CBLI
Manufacturer:
ISSI
Quantity:
1 000
Part Number:
IS43DR16160A-37CBLI
Manufacturer:
ISSI, Integrated Silicon Solution Inc
Quantity:
10 000
Part Number:
IS43DR16160A-37CBLI
Manufacturer:
ISSI
Quantity:
20 000
IS43/46DR83200A, IS43/46DR16160A
41. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of
the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 ps and tJIT(per),max = + 93 ps,
then tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 ps = + 2178 ps and tRPRE,max(derated)
= tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 93 ps = + 2843 ps. (Caution on the min/max usage!)
42. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of
the input clock. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 ps and tJIT(duty),max
= + 93 ps, then tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 ps = + 928 ps and
tRPST,max(derated) = tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 93 ps = + 1592 ps. (Caution on the min/max
usage!)
43. When the device is operated with input clock jitter, this parameter needs to be derated by { -tJIT(duty),max -
tERR(6-10per),max } and { - tJIT(duty),min - tERR(6-10per),min } of the actual input clock. (output deratings are
relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 ps, tERR(6-10per),max =
+ 293 ps, tJIT(duty),min = - 106 ps and tJIT(duty),max = + 94 ps, then tAOF,min(derated) = tAOF,min + { - tJIT(duty),
max - tERR(6-10per),max } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and tAOF,max(derated) = tAOF,max + { -
tJIT(duty),min - tERR(6-10per),min } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps. (Caution on the min/max usage!)
44. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock HIGH pulse width
of 0.5 relative to tCK. tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of
tCH offset present at the DRAM input with respect to 0.5. For example, if an input clock has a worst case tCH of 0.45,
the tAOF,min should be derated by subtracting 0.05 x tCK from it, whereas if an input clock has a worst case tCH of
0.55, the tAOF,max should be derated by adding 0.05 x tCK to it. Therefore, we have;
tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH,min)] x tCK
tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH,max) - 0.5] x tCK
or
tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH,min] x tCK)
tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH,max - 0.5] x tCK)
where tCH,min and tCH,max are the minimum and maximum of tCH actually measured at the DRAM input balls.
45. For tAOFD of DDR2-667/800, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg), average input clock
HIGH pulse width of 0.5 relative to tCK(avg). tAOF,min and tAOF,max should each be derated by the same amount
as the actual amount of tCH(avg) offset present at the DRAM input with respect to 0.5. For example, if an input clock
has a worst case tCH(avg) of 0.48, the tAOF,min should be derated by subtracting 0.02 x tCK(avg) from it, whereas
if an input clock has a worst case tCH(avg) of 0.52, the tAOF,max should be derated by adding 0.02 x tCK(avg) to it.
Therefore, we have;
tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH(avg),min)] x tCK(avg)
tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH(avg),max) - 0.5] x tCK(avg)
or
tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH(avg),min] x tCK(avg))
tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH(avg),max - 0.5] x tCK(avg))
where tCH(avg),min and tCH(avg),max are the minimum and maximum of tCH(avg) actually measured at the DRAM
input balls.
Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and tERR(6-10per).
However tAC values used in the equations shown above are from the timing parameter table and are not derated.
Thus the final derated values for tAOF are;
tAOF,min(derated_final) = tAOF,min(derated) + { - tJIT(duty),max - tERR(6-10per),max }
tAOF,max(derated_final) = tAOF,max(derated) + { - tJIT(duty),min - tERR(6-10per),min }
Integrated Silicon Solution, Inc. — www.issi.com
31
Rev.  A
04/08/2011

Related parts for IS43DR16160A-37CBL