CAT25080LI-G CATALYST SEMICONDUCTOR, CAT25080LI-G Datasheet - Page 4

• Manufacturer Part Number: CAT25080LI-G
• Description: IC, EEPROM, 8KBIT, SERIAL, 10MHZ, DIP-8
• Manufacturer: CATALYST SEMICONDUCTOR

Specifications of CAT25080LI-G

• Memory Size: 8Kbit
• Memory Configuration: 1K X 8 / 512 X 16
• Ic Interface Type: SPI
• Clock Frequency: 10MHz
• Supply Voltage Range: 1.8V To 5.5V
• Memory Case Style: DIP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Description
SI: The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO: The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK: The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAT25080/160.
CS: The chip select input pin is used to enable/disable the
CAT25080/160. When CS is high, the SO output is tri−stated
(high impedance) and the device is in Standby Mode (unless
an internal write operation is in progress). Every
communication session between host and CAT25080/160
must be preceded by a high to low transition and concluded
with a low to high transition of the CS input.
WP: The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
HOLD: The HOLD input pin is used to pause transmission
between host and CAT25080/160, without having to
retransmit the entire sequence at a later time. To pause,
HOLD must be taken low and to resume it must be taken
back high, with the SCK input low during both transitions.
Status Register
number of status and control bits.
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
WREN/WRDI commands. When set to 1, the device is in a
The Status Register, as shown in Table 8, contains a
The RDY (Ready) bit indicates whether the device is busy
The WEL (Write Enable Latch) bit is set/reset by the
SCK
CS
SO
SI
t
CNH
HI−Z
t
SU
t
CSS
VALID
IN
t
t
H
WH
Figure 2. Synchronous Data Timing
t
WL
http://onsemi.com
t
V
t
t
RI
FI
VALID
OUT
4
t
HO
When not used for pausing, the HOLD input should be tied
to V
Functional Description
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8−bit instruction register. The instruction
set and associated op−codes are listed in Table 7.
accomplished by simply providing the READ command and
an address. Writing to the CAT25080/160, in addition to a
WRITE command, address and data, also requires enabling
the device for writing by first setting certain bits in a Status
Register, as will be explained later.
CAT25080/160 will accept any one of the six instruction
op−codes listed in Table 7 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
Write Enable state and when set to 0, the device is in a Write
Disable state.
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
Table 7. INSTRUCTION SET
The CAT25080/160 devices support the Serial Peripheral
Reading data stored in the CAT25080/160
After a high to low transition on the CS input pin, the
The BP0 and BP1 (Block Protect) bits determine which
Instruction
CC
WRITE
WREN
WRSR
RDSR
WRDI
READ
t
CSH
, either directly or through a resistor.
t
V
0000 0100
0000 0101
0000 0001
0000 0010
0000 0110
0000 0011
Opcode
t
DIS
t
CS
t
CNS
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Operation
HI−Z
is