PIC18F452I/L Microchip Technology, PIC18F452I/L Datasheet - Page 326

• Manufacturer Part Number: PIC18F452I/L
• Description: IC, 8BIT MCU, PIC18F, 40MHZ, LCC-44
• Manufacturer: Microchip Technology

Specifications of PIC18F452I/L

• Controller Family/series: PIC18
• No. Of I/o's: 34
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Core Size: 8 Bit
• Program Memory Size: 16 KWords
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18FXX2
DS39564C-page 324
Example SPI Master Mode (CKE = 0) ..................... 278
Example SPI Master Mode (CKE = 1) ..................... 279
Example SPI Slave Mode (CKE = 0) ....................... 280
Example SPI Slave Mode (CKE = 1) ....................... 281
External Clock (All Modes except PLL) .................... 271
First START Bit Timing ............................................ 153
I
I
I
I
I
I
I
I
I
Low Voltage Detect .................................................. 192
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4X2) .............................. 277
Parallel Slave Port (Read) ........................................ 101
Parallel Slave Port (Write) ........................................ 100
PWM Output ............................................................. 122
Repeat START Condition ......................................... 154
RESET, Watchdog Timer (WDT),
Slave Synchronization .............................................. 131
Slaver Mode General Call Address Sequence
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 130
SPI Mode (Slave Mode with CKE = 0) ..................... 132
SPI Mode (Slave Mode with CKE = 1) ..................... 132
Stop Condition Receive or Transmit Mode .............. 158
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock ........................... 275
Timing for Transition Between Timer1 and
Transition Between Timer1 and OSC1
Transition Between Timer1 and OSC1
Transition from OSC1 to Timer1 Oscillator ................ 22
USART Asynchronous Master Transmission ........... 173
USART Asynchronous Master Transmission
USART Asynchronous Reception ............................ 175
USART Synchronous Receive (Master/Slave) ......... 286
USART Synchronous Reception
USART Synchronous Transmission ......................... 177
USART Synchronous Transmission
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 282
C Bus START/STOP Bits ...................................... 282
C Master Mode (Reception, 7-bit Address) ........... 157
C Master Mode (Transmission,
C Slave Mode Timing (10-bit Reception,
C Slave Mode Timing (10-bit Transmission) ......... 143
C Slave Mode Timing (7-bit Reception,
C Slave Mode Timing (7-bit Reception,
C Slave Mode Timing (7-bit Transmission) ........... 141
7 or 10-bit Address) ......................................... 156
SEN = 0) .......................................................... 142
SEN = 0) .......................................................... 140
SEN = 1) .................................................. 146, 147
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 273
(7 or 10-bit Address Mode) .............................. 148
(MCLR Tied to V
(MCLR Not Tied to V
Case 1 ................................................................ 32
Case 2 ................................................................ 32
(MCLR Tied to V
OSC1 (HS with PLL) .......................................... 23
(HS, XT, LP) ....................................................... 22
(RC, EC) ............................................................ 23
(Back to Back) .................................................. 173
(Master Mode, SREN) ...................................... 178
(Master/Slave) .................................................. 286
2
2
C Bus Data ........................................ 284
C Bus START/STOP Bits .................. 284
DD
DD
) ........................................... 33
) ........................................... 32
DD
)
DD
) ......................... 33
Timing Diagrams Requirements
Timing Requirements
Timing Specifications
TRISE Register
TSTFSZ ........................................................................... 251
Two-Word Instructions
TXSTA Register
U
Universal Synchronous Asynchronous
USART ............................................................................. 165
USART Synchronous Transmission
Wake-up from SLEEP via Interrupt .......................... 206
Master SSP I
A/D Conversion ........................................................ 288
Capture/Compare/PWM (CCP1 and CCP2) ............ 276
CLKO and I/O .......................................................... 273
Example SPI Mode (Master Mode, CKE = 0) .......... 278
Example SPI Mode (Master Mode, CKE = 1) .......... 279
Example SPI Mode (Slave Mode, CKE = 0) ............ 280
Example SPI Slave Mode (CKE = 1) ....................... 281
External Clock .......................................................... 271
I
Master SSP I
Parallel Slave Port (PIC18F4X2) ............................. 277
RESET, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock .......................... 275
USART Synchronous Receive ................................. 286
USART Synchronous Transmission ........................ 286
PLL Clock ................................................................ 272
PSPMODE Bit .....................................................95, 100
Example Cases .......................................................... 41
BRGH Bit ................................................................. 168
Receiver Transmitter. See USART
Asynchronous Mode ................................................ 172
Baud Rate Generator (BRG) ................................... 168
Serial Port Enable (SPEN Bit) ................................. 165
Synchronous Master Mode ...................................... 176
Synchronous Slave Mode ........................................ 179
2
C Bus Data (Slave Mode) ..................................... 283
(Through TXEN) .............................................. 177
Timer, Power-up Timer and
Brown-out Reset Requirements ....................... 274
Associated Registers, Receive ........................ 175
Associated Registers, Transmit ....................... 173
Receiver .......................................................... 174
Transmitter ....................................................... 172
Associated Registers ....................................... 168
Baud Rate Error, Calculating ........................... 168
Baud Rate Formula .......................................... 168
Baud Rates for Asynchronous Mode
Baud Rates for Asynchronous Mode
Baud Rates for Synchronous Mode ................. 169
High Baud Rate Select (BRGH Bit) ................. 168
Sampling .......................................................... 168
Associated Registers, Reception ..................... 178
Associated Registers, Transmit ....................... 176
Reception ........................................................ 178
Transmission ................................................... 176
Associated Registers, Receive ........................ 180
Associated Registers, Transmit ....................... 179
Reception ........................................................ 180
Transmission ................................................... 179
(BRGH = 0) .............................................. 170
(BRGH = 1) .............................................. 171
2
2
C Bus START/STOP Bits .................. 284
C Bus Data ........................................ 285
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