PIC18F452I/L Microchip Technology, PIC18F452I/L Datasheet - Page 67

• Manufacturer Part Number: PIC18F452I/L
• Description: IC, 8BIT MCU, PIC18F, 40MHZ, LCC-44
• Manufacturer: Microchip Technology

Specifications of PIC18F452I/L

• Controller Family/series: PIC18
• No. Of I/o's: 34
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Core Size: 8 Bit
• Program Memory Size: 16 KWords
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.0
The Data EEPROM is readable and writable during
normal operation over the entire V
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
There are four SFRs used to read and write the
program and data EEPROM memory. These registers
are:
• EECON1
• EECON2
• EEDATA
• EEADR
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 256 bytes of data EEPROM with
an address range from 0h to FFh.
The EEPROM data memory is rated for high erase/
write cycles. A byte write automatically erases the loca-
tion and writes the new data (erase-before-write). The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature, as well as
from chip to chip. Please refer to parameter D122
(Electrical Characteristics, Section 22.0) for exact
limits.
© 2006 Microchip Technology Inc.
DATA EEPROM MEMORY
DD
range. The data
6.1
The address register can address up to a maximum of
256 bytes of data EEPROM.
6.2
EECON1 is the control register for EEPROM memory
accesses.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the EEPROM write sequence.
Control bits RD and WR initiate read and write opera-
tions, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal opera-
tion. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR), due to the RESET condition forcing the
contents of the registers to zero.
Note:
EECON1 and EECON2 Registers
EEADR
Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.
PIC18FXX2
DS39564C-page 65