JN5148-001 Jennic LTD, JN5148-001 Datasheet
JN5148-001
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JN5148-001 Summary of contents
Page 1
... Data Sheet: JN5148-001 Preliminary IEEE802.15.4 Wireless Microcontroller Overview The JN5148-001 is an ultra low power, high performance wireless microcontroller targeted at ZigBee PRO networking applications. The device features an enhanced 32-bit RISC processor offering high coding efficiency through variable width instructions, a multi-stage instruction pipeline and low power operation with programmable clock speeds ...
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... Internal Power-on Reset 6.2 External Reset 6.3 Software Reset 6.4 Brown-out Detect 6.5 Watchdog Timer 7 Interrupt System 7.1 System Calls 7.2 Processor Exceptions 7.2.1 Bus Error 7.2.2 Alignment 7.2.3 Illegal Instruction 7.2.4 Stack Overflow 7.3 Hardware Interrupts 2 JN-DS-JN5148-001 1v2 Preliminary ...
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... Slave Two-wire Serial Interface 16 Four-Wire Digital Audio Interface 17 Random Number Generator 18 Sample FIFO 19 Intelligent Peripheral Interface 19.1 Data Transfer Format 19.2 JN5148 (Slave) Initiated Data Transfer 19.3 Remote (Master) Processor Initiated Data Transfer © Jennic 2009 JN-DS-JN5148-001 1v2 Preliminary Jennic ...
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... RC Oscillator 22.3.15 Temperature Sensor 22.3.16 Radio Transceiver Appendix A Mechanical and Ordering Information A.1 56-pin QFN Package Drawing A.2 PCB Decal A.3 Ordering Information A.4 Device Package Marking A.5 Tape and Reel Information A.5.1 Tape Orientation and Dimensions 4 JN-DS-JN5148-001 1v2 Preliminary ...
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... B.1.3 Crystal ESR and Required Transconductance B.2 32MHz Oscillator B.3 32kHz Oscillator B.4 JN5148 Module Reference Designs B.4.1 Schematic Diagram B.4.2 PCB Design and Reflow Profile Related Documents RoHS Compliance Status Information Disclaimers Version Control Contact Details © Jennic 2009 JN-DS-JN5148-001 1v2 Preliminary Jennic ...
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... Jennic 1 Introduction The JN5148-001 is an IEEE802.15.4 wireless microcontroller that provides a fully integrated solution for applications using the IEEE802.15.4 standard in the 2.4 - 2.5GHz ISM frequency band [1], including ZigBee PRO. It includes all of the functionality required to meet the IEEE802.15.4 and ZigBee PRO specifications and has additional processor capability to run a wide range of applications including, but not limited to Smart Energy, Automatic Meter Reading, Remote Control, Home and Building Automation, Toys and Gaming ...
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... JTAG hardware debug port User applications access the peripherals using the Integrated Peripherals API. This allows applications to use a tested and easily understood view of the peripherals allowing rapid system development. © Jennic 2009 2 C) supporting master and slave operation JN-DS-JN5148-001 1v2 Preliminary Jennic 7 ...
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... I2S_CLK Audio FIFO I2S_SYNC Interf ace Wireless Transceiv er Security Coprocessor Time Digital Of Baseband Flight Radio Figure 1: JN5148 Block Diagram JN-DS-JN5148-001 1v2 Preliminary SPICLK SPIMOSI SPIMISO SPISEL0 DIO0/SPISEL1 DIO1/SPISEL2/PC0 DIO2/SPISEL3/RFRX DIO3/SPISEL4/RFTX DIO4/CTS0/JTAG_T CK DIO5/RTS0/JTAG_T MS DIO6/TXD0/JTAG_TDO DIO7/RXD0/JTAG_T DI DIO8/T IM0CK_G T/PC1 DIO9/T IM0CAP/32KXTALIN/32KIN DIO10/T IM0OUT /32KXTALOUT ...
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... IBIAS 14 Figure 2: 56-pin QFN Configuration (top view) Note: Please refer to Appendix B.4 JN5148 Module Reference Design for important applications information regarding the connection of the PADDLE to the PCB. © Jennic 2009 VSSA (Paddl e) JN-DS-JN5148-001 1v2 Preliminary Jennic DIO2/SPISEL3/RFRX 42 41 DIO1/SPISEL2/PC0 VB_DIG 40 RESETN ...
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... PC0 RFRX RFTX CTS0 JTAG_TCK RTS0 JTAG_TMS TXD0 JTAG_TDO RXD0 JTAG_TDI PC1 32KXTALIN 32KIN JN-DS-JN5148-001 1v2 Preliminary Signal Description Type 1.8V Regulated supply voltage 3.3V Supplies: VDD1 for analogue, VDD2 for digital 0V Grounds (see appendix A.2 for paddle details) No connect CMOS Reset input 1 ...
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... DAI_WS ADE DAI_SDIN IP_DI JTAG_TDI (optional) DAI_SCK JTAG_TCK DAI_SDOUT JTAG_TMS JTAG_TDO JTAG_TDI (default) JN-DS-JN5148-001 1v2 Preliminary Jennic Signal Description Type CMOS DIO10, Timer0 PWM Output or 32K External Crystal Output CMOS DIO11, Timer1 Clock/Gate Input or Timer2 PWM Output CMOS DIO12, Timer1 Capture Input, ...
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... The radio is a single ended design, requiring a capacitor and just two inductors to match to 50Ω microstrip line to the RF_IN pin. An external resistor (43kΩ) is required between IBIAS and analogue ground to set various bias currents and references within the radio. 12 JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... A schematic view of the digital I/O cell is in Figure 4: DIO Pin Equivalent Schematic. © Jennic 2009 VDD1 Analogue I/O Pin VSSA Figure 3: Analogue I/O Cell JN-DS-JN5148-001 1v2 Preliminary Jennic 13 ...
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... DIO pins retain both their input/output state and output level that was set as sleep commences. If the DIO pins were enabled as inputs and the interrupts were enabled then these pins may be used to wake up the JN5148 from sleep. 14 VDD2 DIO[x] Pin R PROT VSS JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... Additionally possible under software control, to set the speed of the CPU 32MHz. This feature can be used to trade-off processing power against current consumption. © Jennic 2009 JN-DS-JN5148-001 1v2 Preliminary Jennic 15 ...
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... RAM (128kB) 0xF0000000 Unpopulated RAM Echo 0x04000000 Peripherals 0x02000000 0x00020000 ROM (128kB) 0x00000000 Figure 5: JN5148 Memory Map 0x00020000 Spare APIs IEEE802.15.4 Stack Boot Loader Interrupt Manager Interrupt Vectors 0x00000000 Figure 6: Typical ROM contents JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... Figure 8 for connection details. Figure 8: Connecting External Serial Memory © Jennic 2009 CPU Stack (Grows Down) Application MAC Address MAC Data Interrupt Vector Table Figure 7: Typical RAM Contents Serial JN5148 Memory SPISEL0 SS SPIMISO SDO SPIMOSI SDI SPICLK CLK JN-DS-JN5148-001 1v2 Preliminary Jennic 17 ...
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... Integrated Peripherals API Reference Manual (JN-RM-2001).[6] 4.6 Unused Memory Addresses Any attempt to access an unpopulated memory area will result in a bus error exception (interrupt) being generated. 18 Device Number 25VF010A (1Mbyte device) M25P10-A (1Mbyte device), M25P40 (4Mbyte device) Table 1: Supported Flash Memories JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... XTALIN C1 Figure 9: 32MHz Crystal Oscillator Connections 5.1.2 24MHz RC Oscillator An on-chip 24MHz RC oscillator is provided. No external components are required for this oscillator. The electrical specification of the oscillator can be found in section 22.3.14. © Jennic 2009 JN5148 R1 XTALOUT C2 JN-DS-JN5148-001 1v2 Preliminary Jennic 19 ...
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... An externally supplied 32kHz reference clock on the 32KIN input (DIO9) may be provided to the JN5148. This would allow the 32kHz system clock to be sourced from a very stable external oscillator module, allowing more accurate sleep cycle timings compared to the internal RC oscillator. (See section 22.2.3 I/O Characteristics, DIO9 tolerant input) 20 JN5148 32KXTALOUT JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... CPU is allowed to run. VDD Internal RESET RESETN Pin When the supply drops below the power on reset ‘falling’ threshold, it will re-trigger the reset. Use of the external reset circuit show in Figure 12 is suggested. © Jennic 2009 Figure 11: Internal Power-on Reset JN-DS-JN5148-001 1v2 Preliminary Jennic 21 ...
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... For instance, the RC values recommended in section 6.1 may need to be replaced with a suitable reset IC 22 VDD JN5148 18k RESETN 470nF Figure 12: External Reset Generation Reset Internal Reset Figure 13: External Reset JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... The watchdog runs continuously, even during doze, however the watchdog does not operate during sleep or deep sleep, or when the hardware debugger has taken control of the CPU. It will recommence automatically if enabled once the debugger un-stalls the CPU. © Jennic 2009 JN-DS-JN5148-001 1v2 Preliminary Jennic 23 ...
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... Tick timer interrupt asserted Load/store address to non-naturally-aligned location Attempt to execute an unrecognised instruction interrupt asserted System call initiated by b.sys instruction caused by the b.trap instruction or the debug unit Caused by software or hardware reset. Stack overflow Table 2: Interrupt Vectors JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... If while processing an interrupt, a new event occurs at the same or lower priority level, a new external interrupt will not be triggered. However new higher priority event occurs, the external interrupt will again be asserted, interrupting the current interrupt service routine. Once the interrupt service routine is complete, lower priority events can be serviced. © Jennic 2009 JN-DS-JN5148-001 1v2 Preliminary Jennic 25 ...
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... The 2.4 GHz signal from the VCO is then passed to the RF Power Amplifier (PA), whose power control can be selected from one of three settings. The output of the PA drives the antenna via the RX/TX switch 26 Calibration Reference & Bias synth Figure 14: Radio Architecture JN-DS-JN5148-001 1v2 Preliminary Radio ADC sigma delta © Jennic 2009 ...
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... Figure 15 and Figure 16). ADO (DIO[12]) Figure 15 Simple Antenna Diversity Implementation using External RF Switch © Jennic 2009 Antenna A Antenna SEL RF Switch: Single-Pole, Double-Throw (SPDT) SELB COM Device RF Port JN-DS-JN5148-001 1v2 Preliminary Jennic 27 ...
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... Figure 16 Antenna Diversity ADO Signal for TX with Acknowledgement DIO13 can be configured to be ADE, the inverse of ADO. In this configuration, an antenna diversity scheme can be implemented without the need for the inverter shown in Figure 15. 28 TX-RX Cycle 2 nd JN-DS-JN5148-001 1v2 Preliminary TX-RX Cycle (1 Retry) st © Jennic 2009 ...
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... IEEE802.15.4 such as CSMA/CA, GTS without processor intervention including retries and random backoffs. © Jennic 2009 Encrypt Port AES AES Codec Codec Inline Security Decrypt Port Figure 17: Baseband Processor JN-DS-JN5148-001 1v2 Preliminary Jennic Tx/Rx Frame Buffer Protocol Timers Processor Bus 29 ...
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... AES core as a coprocessor to the CPU of the JN5148. To allow the hardware to be shared between the two interfaces an arbiter ensures that the streaming interface to the AES core always has priority, to ensure that in-line processing can take place at any time. 30 JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... When operating in a higher data rate mode, the sensitivity of the radio will be reduced. © Jennic 2009 AES Block AES Encrpytion Encoder Controller JN-DS-JN5148-001 1v2 Preliminary Jennic 31 ...
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... After wake-up the DIO will still be an output with the same value but controlled from the GPIO Data/Direction registers. It can be altered with the software functions that adjust the DIO, or the application may re-configure SPISEL1. Unused DIO pins are recommended to be set as inputs with the pull-up enabled. 32 JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... The interface can transfer from 1 to 32-bits without software intervention and can keep the slave select lines asserted between transfers when required, to enable longer transfers to be performed. © Jennic 2009 Data Buffer Figure 19: SPI Block Diagram JN-DS-JN5148-001 1v2 Preliminary Jennic SPICLK SPI Bus ...
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... The data that is received during this transmission can be read ( bits). If the master simply needs to provide a number of SPICLK transitions to allow data Slave 2 Slave 3 User User Defined Defined SPISEL 1 SPISEL 2 SPISEL 3 SPISEL 4 SPIMOSI 36 JN5148 SPICLK 33 SPIMISO 34 Table 3 SPI Configurations JN-DS-JN5148-001 1v2 Preliminary Slave 4 User Defined © Jennic 2009 ...
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... SPIMISO MSB Figure 21: Example SPI Waveforms – Reading from FLASH device using Mode 0 © Jennic 2009 Instruction Transaction Instruction (0x03 MSB Read Data Bytes Transaction(s) 1 value unused by peripherals MSB Byte 1 Byte 2 JN-DS-JN5148-001 1v2 Preliminary Jennic 24-bit Address 8N LSB Byte N 35 ...
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... Int Enable INT Interrupt Generator Rise = Fall = PWM/Δ−Σ Counter PWM/Δ−Σ Reset System Single Reset Shot Figure 22: Timer Unit Block Diagram JN-DS-JN5148-001 1v2 Preliminary OE S TIMxOUT R PWM/Delta- Sigma © Jennic 2009 ...
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... Therefore, if multiple pulses are seen on TIMxCAP before the counter is stopped only the last pulse width will be stored. © Jennic 2009 prescale value. For example, a prescale value of Rise Fall Figure 23: PWM Output Timings JN-DS-JN5148-001 1v2 Preliminary Jennic 37 ...
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... Figure 25 and Figure 26 illustrate the difference between RTZ and NRZ for the same programmed number of pulses RISE RISE Capture Mode Enabled 9 x Figure 24: Capture Mode 17 clocks. The integrated output will only reach half VDD2 in RTZ mode, JN-DS-JN5148-001 1v2 Preliminary 4 t FALL © Jennic 2009 ...
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... Features include: • 32-bit counter © Jennic 2009 Conversion cycle Conversion cycle 1 Conversion cycle Figure 26: Non-Return to Zero Mode M 1N4007 IRF521 1 pulse/rev JN-DS-JN5148-001 1v2 Preliminary Jennic +12V Tacho 39 ...
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... Optionally runs during sleep periods • Clocked by 32kHz system clock; either 32kHz RC oscillator, 32kHz XTAL oscillator or 32kHz clock input 40 Match Value Match = Counter Reset Enable Mode Control Mode Figure 28: Tick Timer JN-DS-JN5148-001 1v2 Preliminary Tick Timer Interrupt & Int © Jennic 2009 ...
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... For a calibration count of 9000, indicating that the RC oscillator period is running at approximately 35kHz, to time for a period of 2 seconds the timer should be loaded with 71,111 ((10000/9000) x (32000 x 2)) rather than 64000. © Jennic 2009 JN-DS-JN5148-001 1v2 Preliminary Jennic 41 ...
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... The system can work with signals up to 100kHz, with no debounce, or from 5.3kHz to 1.7kHz with debounce. When using debounce the 32kHz clock must be active, so for minimum sleep currents the debounce mode should not be used. 42 JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... Jennic 2009 Divisor Latch Registers ID Line Status Register Line Control Register Receiver FIFO FIFO Control Register Transmitter FIFO Figure 29: UART Block Diagram JN-DS-JN5148-001 1v2 Preliminary Jennic Baud Generator Logic Receiver Logic RXD Receiver Shift Register Transmitter Logic TXD Transmitter Shift Register 43 ...
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... The following example shows the UART connected to a 9-pin connector compatible with a PC. As the JN5148 device pins do not provide the RS232 line voltage, a level shifter is used. JN5148 TXD 46 CTS 44 UART0 RXD 47 RTS 45 Figure 30: JN5148 Serial Communication Link 44 PC COM Port RS232 Lev el Shif ter JN-DS-JN5148-001 1v2 Preliminary Pin Signal DTR DSR 7 RTS 8 CTS 9 RI ...
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... It is possible to prevent all hardware debugging by blowing the relevant Efuse bit. The JTAG interface does not support boundary scan testing recommended that the JN5148 is not connected as part of the board scan chain. © Jennic 2009 DIO Assignment UART0 pins UART1 pins Table 4 Hardware Debugger IO JN-DS-JN5148-001 1v2 Preliminary Jennic 45 ...
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... The number of devices connected to the bus is solely dependent on the bus capacitance limit of 400pF. JN5148 SIF_CLK DIO14 SIF SIF_D DIO15 D1_IN D1_OUT 46 VDD Pullup Resistors CLK1_IN D2_IN CLK1_OUT D2_OUT DEVICE 1 DEVICE 2 Figure 31: Connection Details JN-DS-JN5148-001 1v2 Preliminary CLK2_IN CLK2_OUT © Jennic 2009 ...
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... An interrupt will be generated when arbitration has been lost. © Jennic 2009 Clock held low by Slave Master SIF_CLK Slave SIF_CLK Wired-AND SIF_CLK Figure 32: Clock Stretching Start counting high period Wait State Master1 SIF_CLK Master2 SIF_CLK Wired-AND SIF_CLK JN-DS-JN5148-001 1v2 Preliminary Jennic 47 ...
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... A protocol error has been spotted on the interface 48 Name General Call/Start Byte CBUS address Reserved Reserved Hs-mode master code Reserved 10-bit address JN-DS-JN5148-001 1v2 Preliminary Behaviour Ignored Ignored Ignored Ignored Ignored Ignored Only responded bit address set in address register © Jennic 2009 ...
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... Received data in the Data Buffer will always be padded out with 0’s if the Data Transfer Size is less than 16- bits, and any bits received beyond 16-bits when extra padding is used, will be discarded. In the examples, the polarity shown with Left channel = 0, and the idle state is Right Channel. © Jennic 2009 JN-DS-JN5148-001 1v2 Preliminary Jennic 49 ...
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... R2 Figure 34: I²S Mode Right Left Left MSB-2 LSB MSB MSB Figure 35: Left Justified Mode Right Left Left LSB MSB MSB Figure 36: Right Justified Mode JN-DS-JN5148-001 1v2 Preliminary Right MSB-1 MSB-2 LSB Right MSB-2 LSB Right LSB © Jennic 2009 ...
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... The random bits are generated by sampling the state of the 32MHz clock every 32kHz system clock edge. As these clocks are asynchronous to each other, each sampled bit is unpredictable and hence random. © Jennic 2009 JN-DS-JN5148-001 1v2 Preliminary Jennic 51 ...
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... PWM output with a rising edge generated every time a digital audio transfer is required. The transfer rate is typically configured to be the audio sample rate, e.g. 8kHz. If the transfer rate is too fast or slow data will be transferred correctly between the FIFO and the digital audio block. 52 JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... IP_INT SPIINT IP_DO SPIMISO IP_DI SPIMOSI SPI IP_SEL SPISEL MASTER IP_CLK SPICLK Field Description RSVD Reserved, set to 0 TXQ 1: Data queued for transmission RXRDY 1: Buffer ready to receive data Table 6: IP Status Byte Format JN-DS-JN5148-001 1v2 Preliminary Jennic CPU 53 ...
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... IP_CLK in order to transfer its own message length on IP_DI. The master must continue clocking the interface until sufficient clocks have been generated to send 54 N words of data data length or 0s (8-bit) N words of data data length or 0s (8-bit) JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... JN5148. The master should then deassert IP_SEL to show the transfer is complete. Data can be sent in both directions at once and the master must ensure both transfers have completed before deasserting IP_SEL. © Jennic 2009 JN-DS-JN5148-001 1v2 Preliminary Jennic 55 ...
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... VREF pin. Gain settings for the ADC and DAC are independent of each other. The ADC and DAC are clocked from a common clock source derived from the 16MHz clock 56 Vref ADC Comparator 1 Comparator 2 DAC1 DAC2 Figure 39: Analogue Peripherals JN-DS-JN5148-001 1v2 Preliminary Supply Voltage (VDD1) Internal Reference Vref select Processor Bus © Jennic 2009 ...
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... The end of conversion © Jennic 2009 Maximum Input Range Supply Voltage Range (VDD) 1.2V 1.6V 2.4V 3.2V Sample Switch 5 K ADC front end 8 pF JN-DS-JN5148-001 1v2 Preliminary Jennic 2.2V - 3.6V 2.2V - 3.6V 2.6V - 3.6V 3.4V - 3.6V 57 ...
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... Simultaneous conversions with DAC1 and DAC2 are possible. To use both DACs at the same time it is only necessary to enable them and supply the digital values via the software. The DACs should not be used in single shot mode, but continuous conversion mode only, in order to maintain a steady output voltage. 58 JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... JN5148 from sleep where low current consumption is important. The wakeup action and the configuration for which edge of the comparator output will be active are controlled through software. In sleep mode the negative input signal source, must be configured to be driven from the external pins. © Jennic 2009 JN-DS-JN5148-001 1v2 Preliminary Jennic 59 ...
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... Sleep Mode The JN5148 enters sleep mode through software control. In this mode most of the internal chip functions are shutdown to save power, however the state of DIO pins are retained, including the output values and pull-up enables, 60 JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... VDD supply power domain, including the 32kHz oscillator are stopped. This mode can be exited by a power down, a hardware reset on the RESETN pin DIO event. The DIO event in this mode causes a chip reset to occur. © Jennic 2009 JN-DS-JN5148-001 1v2 Preliminary Jennic 61 ...
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... VDD1, VDD2 Ambient temperature range 62 Min -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -40º Min 2.0V -40ºC JN-DS-JN5148-001 1v2 Preliminary Max 3.6V 1.98V VB_xxx + 0.3V VDD1 + 0.3V Lower of (VDD2 + 2V) and 5.5V VDD2 + 0.3V 150ºC 260ºC 2.0kV 500V Max 3.6V 85ºC ...
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... Typ Max Unit 100 nA JN-DS-JN5148-001 1v2 Preliminary Jennic Notes SPI, GPIOs enabled. When in CPU doze the current related to CPU speed is not consumed. CPU in software doze – radio transmitting CPU in software doze – radio in receive mode ...
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... VDD2 VDD2 x 0.27 230 310 VDD2 0.4 VDD2 0.4 VDD2 0 2 POT t STAB JN-DS-JN5148-001 1v2 Preliminary Unit Notes VDD2 = 3.6V, 25C kΩ VDD2 = 3.0V, 25C VDD2 = 2.2V, 25C VDD2 = 2.0V, 25C V 5V Tolerant I/O only With 4mA load V With 4mA load V ...
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... STAB Figure 42: Externally Applied Reset Typ Max 1.47 1.42 0.84 1.95 2.25 2.65 2. 100 DVDD JN-DS-JN5148-001 1v2 Preliminary Jennic Unit Notes Assumes internal pullup µs resistor value of 100K worst case and ~5pF external capacitance V Minimum voltage to avoid being reset V Rising Falling ...
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... IP_SEL t sss IP_CLK t si IP_DI t lz IP_DO Figure 45: Intelligent Peripheral (SPI Slave) Timing Figure 44: SPI Timing (Master) Min 62.5 16.7 @ 3.3V 18.2 @ 2.7V 21 (SPICLK = 16MHz) 0 (SPICLK<16MHz, mode (SPICLK<16MHz, mode JN-DS-JN5148-001 1v2 Preliminary t SSH Max Unit - ssh t hz © Jennic 2009 ...
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... LOW HIGH t 4.7 - SU:STA t 0.25 - SU:DAT t - 1000 300 SU:STO t 4.7 - BUF 400 b V 0.1VDD - nl V 0.2VDD - nh JN-DS-JN5148-001 1v2 Preliminary Jennic Max Unit - BUF t SU;STO P S Fast Mode Unit Min Max 0 400 kHz 0.6 - µs 1.3 - µs 0.6 - µs 0.6 - µs ...
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... Typ Max Unit 0.84 ms 1.0 ms 0.84 + 0.5* ms program size in kBytes 0.84 ms 0.2 µs 0.29 ms JN-DS-JN5148-001 1v2 Preliminary Generic Unit Min Max 125 - Notes Reached oscillator amplitude threshold Assumes SPI clock to external Flash is 16MHz © Jennic 2009 ...
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... Vref V or 2*Vref See Section 22.3.7 Bandgap Reference 1.2 1 JN-DS-JN5148-001 1v2 Preliminary Jennic Notes at 25º 85ºC -40ºC to 20ºC Notes 500kHz Clock 0 to Vref range Guaranteed monotonic 16MHz input clock, ÷32 Programmable 500kHz Clock with sample period of 2 Switchable ...
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... Lower of 2x(Vdd-1.2 ) and V Vdd-0.2 and 2xVref See Section 22.3.7 Bandgap Reference 1.2 1.6 V kΩ Binary JN-DS-JN5148-001 1v2 Preliminary Notes Guaranteed monotonic 16MHz input clock, programmable prescaler With 10k ohms & 20pF load 2MHz Clock with sample period of 2 Output voltage swing ...
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... Typ Max Unit 1.45 µA 1.25 1.05 32kHz +30% ±250 ppm -0.010 %/°C -1.1 %/V JN-DS-JN5148-001 1v2 Preliminary Jennic Notes +/- 250mV overdrive 10pF load Digital delay can max. of two 16MHz clock periods +/- 250mV overdrive No digital delay Programmable in 3 steps and zero Notes 3.6V 3 ...
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... JN-DS-JN5148-001 1v2 Preliminary Notes This is sensitive to the ESR of the crystal,Vdd and total capacitance at each pin Assuming xtal with ESR of les than 40kohms and CL= 9pF External caps = 15pF (Vdd/2mV pk-pk) see Appendix B Bondpad and package ...
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... Typ Max Unit - 85 °C -1.55 -1.66 mV/°C - ±10 °C - 2.5 °C 855 mV 745 mV °C/LSB 0.182 0.209 JN-DS-JN5148-001 1v2 Preliminary Jennic Notes Notes Includes absolute variation due to manufacturing & temp Typical at 3.0V 25° Vref ADC I/P Range 73 ...
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... Parameter Type 1 Impedance Frequency range 2.400 GHz ESD levels (pin 17) 1) With external matching inductors and assuming PCB layout as in Appendix B.4. 74 Min Typical Max RF Port Characteristics 50ohm 2.485GHz TDB JN-DS-JN5148-001 1v2 Preliminary Notes Single Ended 2.4-2.5GHz © Jennic 2009 ...
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... In three 12dB steps (Note3) dBm Measured conducted into 50ohms <-70 30MHz to 1GHz, -40 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz <-70 10 [2. maximum output power -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, section 6.5.3.1 JN-DS-JN5148-001 1v2 Preliminary Jennic Notes 75 ...
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... Measured conducted into 50ohms <-70 30MHz to 1GHz, -40 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz <-70 9 [2. maximum output power -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, section 6.5.3.1 JN-DS-JN5148-001 1v2 Preliminary Notes © Jennic 2009 ...
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... In three 12dB steps (Note3) dBm Measured conducted into 50ohms <-70 30MHz to 1GHz, -40 1GHz to12.5GHz, The following exceptions apply 1.8 to 1.9GHz & 5.15 to 5.3GHz <-70 10 [2. maximum output power -38 -20 dBc At greater than 3.5MHz offset, as per 802.15.4, section 6.5.3.1 JN-DS-JN5148-001 1v2 Preliminary Jennic Notes 77 ...
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... Jennic Note1: Blocker rejection is defined as the value, when 1% PER is seen with the wanted signal 3dB above sensitivity, as per 802.15.4 section 6.5.3.4 Note2: Channels 11,17,24 low/high values reversed. Note3 extra 2.5dB of attenuation is available if required. 78 JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... Appendix A Mechanical and Ordering Information A.1 56-pin QFN Package Drawing Figure 47: 56-pin QFN Package Drawings © Jennic 2009 JN-DS-JN5148-001 1v2 Preliminary Jennic Controlling Dimension: mm millimetres Symbol Min. Nom. Max. A ------ ------ 0.9 A1 0.00 0.01 0.05 A2 ------ 0.65 0.7 A3 0.20 Ref. b 0.2 0.25 0.3 D 8.00 bsc D1 7 ...
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... The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure will likely result in the JN5148 failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application. 80 Figure 48: PCB Decal JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... Where this Data Sheet is denoted as “Advanced” or “Preliminary”, devices will be either Engineering Samples or Prototypes. Devices of this status are marked with an Rx suffix after the ROM identifier to identify the revision of silicon during these product phases - for example JN5148-001 R1 -T. The Standard Supply Multiple (SSM) for Engineering Samples or Prototypes is 50 units with a maximum of 250 units. ...
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... WW 2 digit week number Where this Data Sheet is denoted as “Advanced” or “Preliminary”, devices will be either Engineering Samples or Prototypes. Devices of this status have an Rx suffix after the software ROM identifier, for example JN5148-001 Jennic JN5148-001 Figure 49: Device Package Marking ...
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... Figure 51 shows the detailed dimensions of the tape used for 8x8mm 56QFN devices. Reference © Jennic 2009 Figure 50: Tape and Reel Orientation Dimensions (mm) 8.30 ±0. 8.30 ±0. 1.10 ±0.10 o 12.00 ±0.10 P 0.30 ±0. 16.00 +0.30/-0.10 Figure 51: Tape Dimensions JN-DS-JN5148-001 1v2 Preliminary Jennic 83 ...
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... All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 6 window design with one window on each side blanked to allow adequate labelling space. Tape Width A B (min) 16 180 1.5min – 10e Ohms Square (min) 13 ±0.2 60 +0.1 –0.0 16.40 Figure 52: Reel Dimensions JN-DS-JN5148-001 1v2 Preliminary W (max) 17.90 © Jennic 2009 ...
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... MIL-L-8835 specification. The MBB has a moisture-sensitivity caution label to indicate the moisture-sensitive classification of the enclosed devices. © Jennic 2009 9 11 – 10e Ohms Square C D (min) N (min) 13 +0.5 -0.2 20.2 100 JN-DS-JN5148-001 1v2 Preliminary Jennic W (min) W (max) 15.90 19.40 85 ...
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... PCB parasitic capacitance. With the recommended layout this is about 1.6pF the on-chip parasitic capacitance and is about 1.4pF typically Similarly for Hence for a 9pF load capacitance, and a tight layout the external capacitors should be 15pF defines the oscillation frequency (series) m × JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... NEG ω × × ⎛ ⎜ ≥ m ⎜ ω × × ⎝ ω × × × =40Ω, C =1pF and square law JN-DS-JN5148-001 1v2 Preliminary Jennic and C with C from the crystal ⎞ ⎟ L ⎟ ⎠ =18pF ( for a load 2.59mA/V. The JN5148 has ...
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... Typ Max 32MHz 40ppm 10Ω 60Ω 6pF 9pF 12pF Load Capacitance 9pF and max ESR 40 Ω 15pF JN-DS-JN5148-001 1v2 Preliminary Notes Including temperature and ageing See below for more details See below for more details CL = 9pF, total external capacitance needs to be 2*CL ...
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... Jennic 2009 32MHz Crystal Oscillator Temperature (C) 32MHz Crystal Oscillator 2.6 2.8 3 Supply Voltage (VDD) JN-DS-JN5148-001 1v2 Preliminary Jennic 60 80 100 3.2 3.4 3.6 89 ...
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... JN5148 XTAL32K_OUT Min Typ Max 32kHz 1.6uA 0.1%/ C 10KΩ 25KΩ 80KΩ 6pF 9pF 12.5pF JN-DS-JN5148-001 1v2 Preliminary Notes Vdd=3v, temp=25 C, load cap =9pF, Rm=25K Vdd=3v See below for more details See below for more details © Jennic 2009 ...
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... Jennic 2009 Current Start-up Time 15pF 1.6uA 0.8Sec 9pF 1.4uA 0.6sec 22pF 2.4uA 1.1sec 2.8 3 3.2 Supply Voltage (VDD Crystal ESR (K ohm) JN-DS-JN5148-001 1v2 Preliminary Jennic Max ESR 70KΩ 80KΩ 35KΩ 3.4 3.6 9pF 12.5pF ...
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... Jennic Support web site (www.jennic.com/support) B.4.1 Schematic Diagram A schematic diagram of the JN5148 PCB antenna reference module is shown in Figure 55. Details of component values and PCB layout constraints can be found in Table 8. Figure 55: JN5148 Printed Antenna Reference Module Schematic Diagram 92 JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... Less than 5mm from U1 pin 35 Less than 5mm from U1 pin 40 Less than 5mm from U1 pin 14 Less than 5mm from U1 pin 15 Adjacent to pin 8 and Y1 pin 1 Adjacent to pin 9 and Y1 pin 3 Not fitted Must be copied directly from the reference design. JN-DS-JN5148-001 1v2 Preliminary Jennic 93 ...
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... The suggested reflow profile is shown in Figure 56. The specific paste manufacturers guidelines on peak flow temperature, soak times, time above liquidus and ramp rates should also be referenced. Figure 56: Recommended Reflow Profile for Lead-free Solder Paste or PPF lead frame 94 JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... The functionality and electrical performance specifications are target values of the design and may be used as a guide to the final specification. Integrated circuits are identified with an Rx suffix, for example JN5148-001R1. Jennic reserves the right to make changes to the product specification at anytime without notice. ...
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... All trademarks are the property of their respective owners. Version Control Version Notes 1.0 12th December 2008 – First issue, released as Advance Information 1.1 15th May 2009 – Major revision 1.2 15th July – Released as Preliminary and revised Electrical Parameters section 96 JN-DS-JN5148-001 1v2 Preliminary © Jennic 2009 ...
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... For the contact details of your local Jennic office or distributor, refer to the Jennic web site: © Jennic 2009 Jennic Ltd Furnival Street Sheffield S1 4QT United Kingdom Tel: +44 (0)114 281 2655 Fax: +44 (0) 114 281 2951 E-mail: info@jennic.com www.jennic.com JN-DS-JN5148-001 1v2 Preliminary Jennic 97 ...