JN5148-001 Jennic LTD, JN5148-001 Datasheet - Page 13

• Manufacturer Part Number: JN5148-001
• Description: 32BIT, MCU, ZIGBEE PRO, 128K RAM, 56QFN
• Manufacturer: Jennic LTD

Specifications of JN5148-001

• No. Of I/o's: 21
• Eeprom Memory Size: 128KB
• Ram Memory Size: 128KB
• Cpu Speed: 32MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 3
• Digital Ic Case Style: QFN
• Core Size: 32bit
• Oscillator Type: External
• Peripherals: ADC, DAC, PWM, Timer
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Jennic
2.2.5 Analogue Peripherals
Several of the analogue peripherals require a reference voltage to use as part of their operations. They can use
either an internal reference voltage or an external reference connected to VREF. This voltage is referenced to
analogue ground and the performance of the analogue peripherals is dependant on the quality of this reference.
There are four ADC inputs, two pairs of comparator inputs and two DAC outputs. The analogue I/O pins on the
JN5148 can have signals applied up to 0.3v higher than VDD1. A schematic view of the analogue I/O cell is shown in
Figure 3: Analogue I/O Cell
In reset and deep sleep, the analogue peripherals are all off and the DAC outputs are in a high impedance state.
In sleep, the ADC and DACs are off, with the DAC outputs in high impedance state. The comparators may optionally
be used as a wakeup source.
Unused ADC and comparator inputs should be left unconnected.
VDD1
Analogue
I/O Pin
Analogue
Peripheral
VSSA
Figure 3: Analogue I/O Cell
2.2.6 Digital Input/Output
Digital I/O pins on the JN5148 can have signals applied up to 2V higher than VDD2 (with the exception of pins DIO9
and DIO10 that are 3V tolerant) and are therefore TTL-compatible with VDD2 > 3V. For other DC properties of these
pins see section 22.2.3 I/O Characteristics.
When used in their primary function all Digital Input/Output pins are bi-directional and are connected to weak internal
pull up resistors (40kΩ nominal) that can be disabled. When used in their secondary function (selected when the
appropriate peripheral block is enabled through software library calls) then their direction is fixed by the function. The
pull up resistor is enabled or disabled independently of the function and direction; the default state from reset is
enabled.
A schematic view of the digital I/O cell is in Figure 4: DIO Pin Equivalent Schematic.
© Jennic 2009
JN-DS-JN5148-001 1v2
13
Preliminary