LA-ISPPAC-POWR1014A-01TN48E LATTICE SEMICONDUCTOR, LA-ISPPAC-POWR1014A-01TN48E Datasheet - Page 2

• Manufacturer Part Number: LA-ISPPAC-POWR1014A-01TN48E
• Description: IC, PROG POWER SUPPLY SUPERVISOR TQFP-48
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LA-ISPPAC-POWR1014A-01TN48E

• Input Voltage: 4.5V
• Supply Voltage Range: 2.8V To 3.96
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +105°C
• Frequency: 25MHz
• No. Of Macrocells: 24
• Termination Type: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
MOSFET drivers. In high-voltage mode these outputs can provide up to 8V for driving the gates of n-channel MOS-
FETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate
for both ramp up and ramp down.
The LA-ispPAC-POWR1014/A incorporates a 24-macrocell CPLD that can be used to implement complex state
machine sequencing for the control of multiple power supplies as well as combinatorial logic functions. The status
of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as
inputs by the CPLD array, and all digital outputs may be controlled by the CPLD. Four independently programmable
timers can create delays and time-outs ranging from 32µs to 2 seconds. The CPLD is programmed using Logi-
Builder™, an easy-to-learn language integrated into the PAC-Designer
monitor the status of any of the analog input channel comparators or the digital inputs.
The on-chip 10-bit A/D converter is used to monitor the V
POWR1014A device.
The I
inputs, read back the status of each of the V
control the output pins (LA-ispPAC-POWR1014A only).
Figure 1. LA-ispPAC-POWR1014/A Block Diagram
2
C bus/SMBus interface allows an external microcontroller to measure the voltages connected to the V
VMON10
VMON1
VMON2
VMON3
VMON4
VMON5
VMON6
VMON7
VMON8
VMON9
IN1
IN2
IN3
IN4
*LA-ispPAC-POWR1014A only.
ADC*
JTAG LOGIC
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
MON
OSCILLATOR
comparator and PLD outputs, control logic signals IN2 to IN4 and
24 MACROCELLS
CONTROL LOGIC*
CLOCK
MEASUREMENT
53 INPUTS
CPLD
2
MON
TIMERS
(4)
voltage through the I
®
software. Control sequences are written to
INTERFACE
I
2
C
2
C bus of the LA-ispPAC-
HVOUT1
HVOUT2
OUT3/(SMBA*)
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
MON