SI9181DQ-AD-T1-E3 Vishay, SI9181DQ-AD-T1-E3 Datasheet - Page 10

• Manufacturer Part Number: SI9181DQ-AD-T1-E3
• Description: IC, ADJ LDO REG, 1.5V TO 5V 0.6A 8-TSSOP
• Manufacturer: Vishay

Specifications of SI9181DQ-AD-T1-E3

• Primary Input Voltage: 6V
• Output Voltage Adjustable Range: 1.5V To 5V
• Dropout Voltage Vdo: 150mV
• No. Of Pins: 8
• Output Current: 600mA
• Operating Temperature Range: -40°C To +85°C
• Number Of Outputs: 1
• Polarity: Positive
• Input Voltage Max: 6 V
• Output Voltage: 1.5 V to 5 V
• Output Type: Adjustable
• Dropout Voltage (max): 0.25 V at 200 mA
• Line Regulation: 0.18 % / V
• Load Regulation: 30 mV
• Maximum Power Dissipation: 0.833 W
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DETAILED DESCRIPTION
The Si9181 is a low drop out, low quiescent current, and very
linear regulator family with very fast transient response. It is
primarily designed for battery powered applications where
battery run time is at a premium. The low quiescent current
allows extended standby time while low drop out voltage
enables the system to fully utilize battery power before
recharge. The Si9181 is a very fast regulator with bandwidth
exceeding 50 kHz while maintaining low quiescent current at
light load conditions. With this bandwidth, the Si9181 is the
fastest LDO available today. The Si9181 is stable with any
output capacitor type from 1 mF to 10.0 mF. However, X5R or
X7R ceramic capacitors are recommended for best output
noise and transient performance.
V
V
is not critical as long as the input supply has low enough source
impedance. For practical circuits, a 1.0-mF or larger ceramic
capacitor is recommended. When the source impedance is
not low enough and/or the source is several inches from the
Si9181, then a larger input bypass capacitor is needed. It is
required that the equivalent impedance (source impedance,
wire, and trace impedance in parallel with input bypass
capacitor impedance) must be smaller than the input
impedance of the Si9181 for stable operation. When the
source impedance, wire, and trace impedance are unknown,
it is recommended that an input bypass capacitor be used of
a value that is equal to or greater than the output capacitor.
V
V
capacitor from V
any value from 1.0 mF to 10.0 mF. A ceramic capacitor with
X5R or X7R dielectric type is recommended for best output
noise, line transient, and load transient performance.
GND
Ground is the common ground connection for V
It is also the local ground connection for C
SENSE or ADJ, and SD.
SENSE or ADJ
SENSE is used to sense the output voltage. Connect SENSE
to V
version, use a resistor divider R1 and R2, connect R1 from
V
25-kW to 150-kW range for low power consumption, while
maintaining adequate noise immunity.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and
Package Reliability represent a composite of all qualified locations.
http://www.vishay.com/ppg?71119.
www.vishay.com
10
Si9181
Vishay Siliconix
IN
IN
OUT
OUT
OUT
OUT
is the input supply pin. The bypass capacitor for this pin
is the output voltage of the regulator. Connect a bypass
to ADJ and R2 from ADJ to ground. R2 should be in the
for the fixed voltage version. For the adjustable output
OUT
to ground. The output capacitor can be
NOISE
IN
and V
, DELAY,
For related documents such as package/tape drawings, part marking, and reliability data, see
OUT
.
The formula below calculates the value of R1, given the
desired output voltage and the R2 value,
SHUTDOWN (SD)
SD controls the turning on and off of the Si9181. V
guaranteed to be on when the SD pin voltage equals or is
greater than 1.5 V. V
pin voltage equals or is less than 0.4 V. During shutdown
mode, the Si9181 will draw less than 2-mA current from the
source. To automatically turn on V
applied, tie the SD pin to V
ERROR
ERROR is an open drain output that goes low when V
less than 5% of its normal value. As with any open drain output,
an external pull up resistor is needed. When a capacitor is
connected from DELAY to GROUND, the error signal transition
from low to high is delayed (see Delay section). This delayed
error signal can be used as the power-on reset signal for the
application system. (Refer to Figure 4.)
The ERROR pin is disconnected if not used.
DELAY
A capacitor from DELAY to GROUND sets the time delay for
ERROR going from low to high state. The time delay can be
calculated using the following formula:
The DELAY pin should be an open circuit if not used.
C
For low noise application, connect a high frequency ceramic
capacitor from C
or X7R is recommended.
NOISE
R1 +
T
V
delay
ADJ
is nominally 1.215 V.
+
V
OUT
V
ADJ
* V
V
I
delay
NOISE
ADJ
C
ADJ
delay
OUT
to ground. A 0.01-mF or a 0.1-mF X5R
R2
is guaranteed to be off when theSD
IN
.
OUT
S-50955—Rev. F, 16-May-05
whenever the input is
Document Number: 71119
(1)
(2)
OUT
OUT
is
is