MB85RC64PNF-G-JNE1 Fujitsu, MB85RC64PNF-G-JNE1 Datasheet - Page 2

• Manufacturer Part Number: MB85RC64PNF-G-JNE1
• Description: IC, MEMORY, FRAM, 64K, 12C, 8SOP
• Manufacturer: Fujitsu

Specifications of MB85RC64PNF-G-JNE1

• Memory Size: 64Kbit
• Access Time: 900ns
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Interface: I2C, Serial, 2 Wire
• Memory: RoHS Compliant
• Memory Configuration: 8K X 8
• Nvram Features: I2C Bus Specification Version 2.1 Compliant, Fully Controllable By SCL And SDA Ports
• Interface Type: I2C, Serial, 2-Wire
• Rohs Compliant: Yes

MB85RC64
2
■ PIN ASSIGNMENT
■ PIN FUNCTIONAL DESCRIPTIONS
Number
1 to 3
Pin
4
5
6
7
8
Pin Name
A0 to A2
SDA
VDD
VSS
SCL
WP
VSS
Device Address
The MB85RC64 can be connected to the same data bus up to 8 devices. Device
addresses are used in order to identify each of the devices. Connect these pins to
VDD or VSS externally. Only if the combination of VDD and VSS matches a device,
an address and a code inputted from the SDA pin, the device operates. In the open
pin state, A0, A1, and A2 are pulled-down and recognized as “L”.
Ground
Serial Data I/O
This is an I/O pin of serial data for performing bidirectional communication of ad-
dress and writing or reading data of FRAM memory cell array. It is an open drain
output that may be wired OR with other open drain or open collector signals on the
bus, so a pull-up resistance is required to be connected to the external circuit.
Serial Clock
This is a clock input pin for input/output serial data. Data is sampled on the rising
edge of the clock and output on the falling edge.
Write Protect
When WP is “H”, writing operation is disabled. When WP is “L”, the entire memory
region can be overwritten. Reading operation is always enabled regardless of the
WP input level. If WP is not forced as “H” or “L”, WP is internally pull-downed.
Supply Voltage
A0
A1
A2
1
2
3
4
(FPT-8P-M02)
(TOP VIEW)
Functional Description
8
7
6
5
VDD
WP
SCL
SDA
DS05-13109-1E