MB85RC64PNF-G-JNE1 Fujitsu, MB85RC64PNF-G-JNE1 Datasheet - Page 7

• Manufacturer Part Number: MB85RC64PNF-G-JNE1
• Description: IC, MEMORY, FRAM, 64K, 12C, 8SOP
• Manufacturer: Fujitsu

Specifications of MB85RC64PNF-G-JNE1

• Memory Size: 64Kbit
• Access Time: 900ns
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOP
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Interface: I2C, Serial, 2 Wire
• Memory: RoHS Compliant
• Memory Configuration: 8K X 8
• Nvram Features: I2C Bus Specification Version 2.1 Compliant, Fully Controllable By SCL And SDA Ports
• Interface Type: I2C, Serial, 2-Wire
• Rohs Compliant: Yes

DS05-13109-1E
■ DATA STRUCTURE
• Data Structure Diagram
■ FRAM ACKNOWLEDGE -- POLLING NOT REQUIRED
*: As to E
■ WRITE PROTECT (WP)
Note : The WP pin is pulled down internally to VSS, therefore if the WP pin is open, the pin status is detected as
SDA
SCL
In the I
the start condition. After confirming the acknowledge response at the slave, the I
memory address to the I
“L”. After this operation, the I/O data follows in units of 8 bits, with the acknowledge “L” output after every 8bits.
It is determined by the R/W code whether the data line is driven by the master or the slave. For a write operation
the slave will accept 8bits from the master then send an acknowledge. If the master detects the acknowledge,
the master will transfer the next 8bits. For a read operation the slave will place 8bits on the I
for an acknowledge from the master.
The MB85RC64 performs write operations at the same speed as read operations, so any waiting time for an
ACK polling* does not occur. The write cycle takes no additional time.
places NAK condition on the bus as of “not acknowledged” during the writing programming period. The busy
status for the write programming is given from 9th ACK bit. That “done” condition is placed onto I
E
The memory array can be write protected using the WP pin. When the WP is set to “H”, the entire memory map
will be write protected. When the write protect pin is “L”, all addresses may be overwritten.
2
PROM I
Low (write enabled).
2
C bus, the acknowledge “L” is output on the 9th bit after the 8 bits of the device and address word following
2
PROM, the Acknowledge Polling is performed as a progress check in the write programming step. It
Start
2
S
C device and your program had to poll the bus in order to sense that condition.
1
1
2
0
2
C slave. When the memory address input ends, the slave again outputs the acknowledge
3
1
4
0
A2
5
A1
6
A0
7
R/W
8
ACK
A
9
1
S
A
2
ACK
Access from master
Start Condition
Access from slave
2
. .
. .
C master outputs 8bits x2
MB85RC64
2
C bus, then wait
2
C bus by
7