CS5102A-BL Cirrus Logic Inc, CS5102A-BL Datasheet - Page 18

• Manufacturer Part Number: CS5102A-BL
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5102A-BL

• Input Channels Per Adc: 2
• Mounting Type: Surface Mount
• No. Of Channels: 2
• Power Rating: 44mW
• Supply Voltage Min: 4.5V
• Peak Reflow Compatible (260 C): No
• Sample Rate: 20kSPS
• Supply Voltage Max: 5.5V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

fine-charge until HOLD goes low. To get an accu-
rate sample using the CS5101A, at least 750 ns of
coarse-charge, followed by 1.125 µs of fine-charge
is required before initiating a conversion. If coarse
charge is not invoked, then up to 25 µs should be
allowed after a step change input for proper acqui-
sition. To get an accurate sample using the
CS5102A, at least 3.75 µs of coarse-charge, fol-
4.3
The CS5101A and CS5102A can operate either
from an externally-supplied master clock, or from
their own crystal oscillator (with a crystal). To en-
able the internal crystal oscillator, simply tie a crys-
tal across the XOUT and CLKIN pins and add 2
capacitors and a resistor, as shown on the system
connection diagram in Figure 9.
Calibration and conversion times directly scale to
the master clock frequency. The CS5101A can op-
erate with clock or crystal frequencies up to 9.216
MHz (8.0 MHz in FRN mode). This allows maxi-
mum throughput of up to 50 kSps per channel in
dual-channel operation, or 100 kSps in a single-
channel configuration. The CS5102A can operate
with clock or crystal frequencies up to 2.0 MHz (1.6
MHz in FRN mode). This allows maximum
throughput of up to 10 kSps per channel in dual-
channel operation, or 20 kSps in a single channel
configuration. For 16-bit performance a 1.6 MHz
clock is recommended. This 1.6 MHz clock yields
a maximum throughput of 20 kSps in a single-
channel configuration.
18
Master Clock
C L K IN
C R S /F IN
In te rn al
S tatus
TR K 1 or
T R K 2
H O L D
** A pplies to 51 02A
* A pplies to 5101A
C onv.
Figure 4. Coarse/Fine Charge Control
C o arse
2 clk
M in: 750 ns*
6 clk
F in e C hg.
3.75 µ s**
M in : 1 .1 2 5 µ s*
5 .62 5 µ s**
C o arse
lowed by 5.625 µs of fine-charge is required before
initiating a conversion (see Figure 4). If coarse
charge is not invoked, then up to 125 µs should be
allowed after a step change input for proper acqui-
sition. The CRS/FIN pin must be low prior to HOLD
becoming active and be held low during conver-
sion.
4.4
When HOLD goes low, the analog sample is cap-
tured immediately. The HOLD signal is latched by
the next falling edge of CLKIN, and conversion
then starts on the subsequent rising edge. If HOLD
is asynchronous to CLKIN, then there will be a 1.5-
CLKIN-cycle uncertainty as to when conversion
starts. Considering the CS5101A with an 8 MHz
CLKIN, with a 100 kHz HOLD signal, then this 1.5-
CLKIN uncertainty will result in a 1.5-CLKIN-period
possible reduction in fine charge time for the next
conversion.
This reduced fine charge time will be less than the
minimum specification. If the CLKIN frequency is
increased slightly (for example, to 8.192 MHz) then
sufficient fine charge time will always occur. The
maximum frequency for CLKIN is specified at
9.216 MHz. It is recommended that for asynchro-
nous operation at 100 kSps, CLKIN should be be-
tween 8.192 MHz and 9.216 MHz.
Asynchronous Sampling
Considerations
Fine C hg.
CS5101A CS5102A
C on v.
DS45F6