CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet - Page 15

• Manufacturer Part Number: CS5501-BS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5501-BS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

complete the current data bit output and go to a
high impedance state when SCLK goes low.
Synchronous External Clocking Mode
When operated in the SEC mode (MODE pin tied
to DGND), the CS5501/CS5503 outputs the data
in its serial port at a rate determined by an exter-
nal clock which is input into the SCLK pin. In
this mode the output port will be updated every
1024 CLKIN cycles. DRDY will go low when
new data is loaded into the output port. If CS is
not active, DRDY will return positive 1020
CLKIN cycles later and remain so for four
CLKIN cycles. If CS is taken low it will be rec-
ognized immediately unless it occurs while
DRDY is high for the four clock cycles. As soon
as CS is recognized, the SDATA output will come
out of its high-impedance state and present the
MSB data bit. The MSB data bit will remain pre-
sent until a falling edge of SCLK occurs to
advance the output to the MSB-1 bit. If the CS
and external SCLK are operated asynchronously
to CLKIN, errors can result in the output data un-
less certain precautions are taken. If CS is
activated asynchronously, it may occur during the
four clock cycles when DRDY is high and there-
fore not be recognized immediately. To be certain
that data misread errors will not result if CS oc-
curs at this time, the SCLK input should not
transition high to latch the MSB until four
CLKIN cycles plus 160 ns after CS is taken low.
DS31F2
SDATA (o)
DRDY (o)
SCLK (i)
CS (i)
Figure 6. Synchronous External-Clocking (SEC) Mode Timing
**
*
Hi-Z
CS5501
CS5503
(MSB)
B15*
B19**
B14*
B18**
This insures that CS will be recognized and the
MSB bit will become stable before the SCLK
transitions positive to latch the MSB data bit.
When SCLK returns low the serial port will pre-
sent the MSB-1 data bit on its output.
Subsequent cycles of SCLK will advance the data
output. When all data bits are clocked out, DRDY
will then go high and the SDATA output will go
into a high impedance state. If the CS input goes
low and all of the data bits are not clocked out of
the port, filter cycles will continue to occur but
the output serial port will not be updated with
new data (DRDY will remain low). If CS is taken
high at any time, the SDATA output pin will go to
a high impedance state. If any of the data bits in
the serial port have not been clocked out, they
will remain available until DRDY returns high for
four clock cycles. After this DRDY will fall and
the port will be updated with a new 16-bit word
in the CS5501 or 20-bit word in the CS5503. It
is acceptable to clock out less than all possible
data bits if CS is returned high to allow the port
to be updated. Figure 6 illustrates the serial port
timing in the SEC mode.
Asynchronous Communication Mode (CS5501
Only)
In the CS5501, the AC mode is activated when
the MODE pin is tied to VD- (-5 V). When oper-
ating in the AC mode the CS5501 is designed to
B1
(LSB)
B0
Hi-Z
CS5501/CS5503
15