CS61884-IQZ Cirrus Logic Inc, CS61884-IQZ Datasheet - Page 40

• Manufacturer Part Number: CS61884-IQZ
• Description: IC,PCM TRANSCEIVER,OCTAL,CEPT PCM-30/E-1,QFP,144PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS61884-IQZ

• Rohs Compliant: YES

14.22 AIS Interrupt Status Register (15h)
14.23 AWG Broadcast Register (16h)
14.24 AWG Phase Address Register (17h)
14.25 AWG Phase Data Register (18h)
14.26 AWG Enable Register (19h)
40
[7:0]
[7:0]
[7:5]
[4:0]
[6:0]
[7:0]
BIT
BIT
BIT
BIT
BIT
[7]
AWGD [6:0]
AWGN 7-0
AWGB 7-0
AISI 7-0
PA[4:0]
AWGA
NAME
NAME
NAME
NAME
NAME
RSVD
The AWG enable register is used for selecting the source of the customized transmission
pulse-shape. Setting bit n to “1” in this register selects the AWG as the source of the output
pulse shape for channel n. When bit n is set to “0” the pre-programmed pulse shape in the
ROM is selected for transmission on channel n. (Refer to
(See Section 15 on page 43). Register bits default to 00h after power-up or reset.
Bit n is set to “1” to indicate a change of status of bit n in the AIS Status Register. The bits in
this register indicate which channel changed in status since the last cleared AIS interrupt.
Register bits default to 00h after power-up or reset.
Setting bit n to “1” causes the phase data in the AWG Phase Data Register to be written to
the corresponding channel or channels simultaneously. (Refer to
erator
These bits specify the target channel 0-7. (Refer to
Section 15 on page 43). Register bits default to 00h after power-up or reset.
These bits specify 1 of 24 (E1) or 26/28 (T1/J1) phase sample address locations of the AWG,
that the phase data in the AWG Phase Data Register is written to or read from. The other
locations in each channel’s phase sample addresses are not used, and should not be
accessed. Register bits default to 00h after power-up or reset.
These bits are used for the pulse shape data that will be written to the AWG phase location
specified by the AWG Phase Address Register. The value written to or read from this register
will be written to or read from the AWG phase sample location specified by the AWG Phase
Address register. A software reset through the Software Reset Register does not effect the
contents of this register. The data in each phase is a 7-bit 2’s complement number (the max-
imum positive value is 3Fh and the maximum negative value is 40h). (Refer to
Waveform Generator
power-up.
(See Section 15 on page 43). Register bits default to 00h after power-up or reset.
(See Section 15 on page 43). Register bits default to 00h after
RESERVED (This bit must be set to 0.)
Description
Description
Description
Description
Description
Arbitrary Waveform Generator
Arbitrary Waveform Generator
Arbitrary Waveform Gen-
CS61884
Arbitrary
DS485F1
(See