DSPIC30F4012T-30I/SO Microchip Technology, DSPIC30F4012T-30I/SO Datasheet - Page 6

• Manufacturer Part Number: DSPIC30F4012T-30I/SO
• Description: IC,DSP,16-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4012T-30I/SO

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4012T30IS

dsPIC30F4011/4012
7. Module: Interrupt Controller – Sequential
EXAMPLE 5:
EXAMPLE 6:
EXAMPLE 7:
DS80215K-page 6
.include
...
DISI#2 ; protect the disable of INT1
BCLRIEC1, #INT1IE; disable interrupt 1
...
.include
...
__asm__ volatile (“DISI #0x1FFF”);
SRbits.IPL = 0x5;
DISICNT = 0x0;
#define DISI_PROTECT(X) {\
DISI_PROTECT(SRbits.IPL = 0x5);
When interrupt nesting is enabled (or NSTDIS
(INTCON1<15>) bit is ‘0’), the following sequence
of events will lead to an address error trap. The
generic terms “Interrupt 1” and “Interrupt 2” are
used to represent any two enabled dsPIC30F
interrupts.
1. Interrupt 1 processing begins.
2. Interrupt 1 is negated by user software by one
3. Interrupt 2 occurs with a priority higher than
__asm__ volatile (“DISI #0x1FFF”);\
X;
DISICNT = 0; }
of the following methods:
- CPU IPL is raised to Interrupt 1 IPL level or
- Interrupt 1 IPL is lowered to CPU IPL level or
- Interrupt 1 is disabled (Interrupt 1 IE bit set
- Interrupt 1 flag is cleared
Interrupt 1.
to ‘0’) or
higher or
lower or
; next instruction protected by DISI
Interrupts
“p30fxxxx.inc”
“p30fxxxx.h”
USING DISI
RAISING CPU INTERRUPT PRIORITY LEVEL
USING MACRO
\
// safely modify the CPU IPL
// protect CPU IPL modification
// set CPU IPL to 5
// remove DISI protection
Work around
The user may disable interrupt nesting or execute
a DISI instruction before modifying the CPU IPL
or Interrupt 1 setting. A minimum DISI value of 2
is required if the DISI is executed immediately
before the CPU IPL or Interrupt 1 is modified, as
shown in Example 5. If the MPLAB C30 compiler
is being used, one must inspect the Disassembly
Listing in the MPLAB IDE file to determine the
exact number of cycles to disable level 1-6
interrupts. One may use a large DISI value and
then set the DISICNT register to zero, as shown in
Example 6. A macro may also be used to perform
this task, as shown in Example 7.
© 2008 Microchip Technology Inc.