DSPIC30F4012T-30I/SO Microchip Technology, DSPIC30F4012T-30I/SO Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F4012T-30I/SO
• Description: IC,DSP,16-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F4012T-30I/SO

• Rohs Compliant: YES
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 48KB (16K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: DSPIC30F4012T30IS

dsPIC30F4011/4012
TABLE 2:
DS80454D-page 2
Operations
Note 1:
Controller
Compare
Compare
Interrupt
Module
Output
Output
Sleep
Mode
I
PWM
CPU
CPU
CPU
CPU
ADC
ADC
PSV
2
PLL
PLL
QEI
I/O
C™
Only those issues indicated in the last column apply to the current silicon revision.
Debug Mode
Modification
Sleep Mode
PWM Mode
Slave Mode
Instructions
SFR Writes
Generation
Nested DO
MAC Class
Instruction
Instruction
Sampling
4x Mode
8x Mode
Interrupt
Feature
Address
SILICON ISSUE SUMMARY
with ±4
DAW.b
Loops
DISI
Rate
—
—
—
—
Number
Item
10.
12.
13.
14.
15.
16.
17.
11.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Sequential MAC instructions, which prefetch data from Y data
space using ±4 address modification, will cause an address
error trap.
The Decimal Adjust instruction, DAW.b, may improperly
clear the Carry bit, C (SR<0>).
Writes to certain unimplemented address locations can
affect I/O Port register values.
In certain instructions, fetching one of the operands from
program memory using Program Space Visibility (PSV) will
corrupt specific bits in the STATUS Register, SR.
When using two DO loops in a nested fashion, terminating
the inner-level DO loop by setting the EDT bit
(CORCON<11>) will produce unexpected results.
The 4x PLL mode of operation may not function correctly for
certain input frequencies.
An interrupt occurring immediately after modifying the CPU
IPL, interrupt IPL, interrupt enable or interrupt flag may
cause an address error trap.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
Output compare will produce a glitch when loading 0% duty
cycle in PWM mode. It will also miss the next compare after
the glitch.
The Output Compare module will produce a glitch on the
output when an I/O pin is initially set high and the module is
configured to drive the pin low at a specified time.
ADC event triggers from the INT0 pin will not wake-up the
device from Sleep mode if the SMPI bits are non-zero.
If 8x PLL mode is used, the input frequency range is 5 MHz-
10 MHz instead of 4 MHz-10 MHz.
The 10-bit Analog-to-Digital Converter (ADC) has a
maximum sampling rate of 750 ksps.
The Quadrature Encoder Interface (QEI) module does not
generate an interrupt in a particular overflow condition.
Execution of the Sleep instruction (PWRSAV #0) may cause
incorrect program operation after the device wakes up from
Sleep. The current consumption during Sleep may also
increase beyond the specifications listed in the device data
sheet.
The I
as an I
PTMR does not continue counting down after halting code
execution in Debug mode.
2
C module loses incoming data bytes when operating
2
C slave.
Issue Summary
© 2010 Microchip Technology Inc.
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(1)
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